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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td61 bits<16> Inst;
75 bits<16> Inst;
87 bits<16> Inst;
100 bits<16> Inst;
114 bits<16> Inst;
127 bits<16> Inst;
139 bits<16> Inst;
150 bits<16> Inst;
161 bits<16> Inst;
172 bits<16> Inst;
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H A DMicroMips32r6InstrFormats.td40 bits<16> Inst;
50 bits<16> Inst;
60 bits<16> Inst;
72 bits<32> Inst;
85 bits<32> Inst;
96 bits<16> Inst;
107 bits<16> Inst;
119 bits<32> Inst;
133 bits<32> Inst;
147 bits<32> Inst;
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H A DMipsMSAInstrFormats.td37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
50 let Inst{19-16} = m;
52 let Inst{10-6} = wd;
63 let Inst{20-16} = m;
65 let Inst{10-6} = wd;
75 let Inst{22} = 0b0;
76 let Inst{21-16} = m;
120 let Inst{16} = df;
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H A DMipsInstrFormats.td179 bits<32> Inst;
193 bits<32> Inst;
208 bits<32> Inst;
221 bits<32> Inst;
236 bits<32> Inst;
249 bits<32> Inst;
265 bits<32> Inst;
281 bits<32> Inst;
293 bits<32> Inst;
306 bits<32> Inst;
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H A DMicroMipsDSPInstrFormats.td30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
41 let Inst{25-21} = rt;
42 let Inst{20-16} = rs;
43 let Inst{15-6} = op;
53 let Inst{25-21} = rt;
54 let Inst{20-16} = rs;
55 let Inst{15-14} = ac;
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H A DMips32r6InstrFormats.td181 bits<32> Inst;
196 bits<32> Inst;
207 bits<32> Inst;
223 bits<32> Inst;
238 bits<32> Inst;
252 bits<32> Inst;
264 bits<32> Inst;
276 bits<32> Inst;
288 bits<32> Inst;
300 bits<32> Inst;
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H A DMipsDSPInstrFormats.td72 let Inst{25-21} = rs;
73 let Inst{20-16} = rt;
74 let Inst{15-11} = rd;
75 let Inst{10-6} = op;
85 let Inst{25-21} = rs;
86 let Inst{20-16} = 0;
87 let Inst{15-11} = rd;
101 let Inst{15-11} = 0;
141 let Inst{25-21} = 0;
263 let Inst{10-6} = 0;
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H A DMipsMTInstrFormats.td40 bits<32> Inst;
45 let Inst{20-16} = rt;
54 bits<32> Inst;
63 let Inst{20-16} = rt;
64 let Inst{15-11} = rd;
66 let Inst{5} = u;
67 let Inst{4} = h;
73 bits<32> Inst;
79 let Inst{25-21} = rs;
80 let Inst{20-16} = rt;
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td13 let Inst{12-8} = Vu32{4-0};
17 let Inst{4-0} = Vdd32{4-0};
21 let Inst{11-5} = Ii{6-0};
25 let Inst{1-0} = Pd4{1-0};
33 let Inst{1-0} = Pd4{1-0};
38 let Inst{7-1} = Ii{8-2};
45 let Inst{8-8} = n1{0-0};
50 let Inst{7-7} = Ii{0-0};
52 let Inst{11-8} = II{5-2};
53 let Inst{6-5} = II{1-0};
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/llvm-project-15.0.7/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp67 assert((isADR(Inst) || isADRP(Inst)) && "Not an ADR instruction"); in getADRReg()
172 return isLDRB(Inst) || isLDRH(Inst) || isLDRW(Inst) || isLDRX(Inst); in isLoad()
250 if (isADR(Inst) || isADRP(Inst)) in evaluateAArch64MemoryOperand()
294 if (isADR(Inst) || isADRP(Inst)) { in replaceMemOperandDisp()
364 if (isConditionalBranch(Inst) || isADR(Inst) || isADRP(Inst)) in getSymbolRefOperandNum()
449 assert((isIndirectBranch(Inst) || isIndirectCall(Inst)) && in evaluateBranch()
461 assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) && in replaceBranchTarget()
806 if (isTB(Inst) || isCB(Inst)) { in reverseBranchCondition()
807 Inst.setOpcode(getInvertedBranchOpcode(Inst.getOpcode())); in reverseBranchCondition()
861 Inst.clear(); in createTrap()
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/llvm-project-15.0.7/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp262 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
265 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
268 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
271 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
274 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
277 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
280 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
283 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
310 Inst.setOpcode(XCore::LSS_3r); in Decode2OpInstructionFail()
313 Inst.setOpcode(XCore::LSU_3r); in Decode2OpInstructionFail()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp188 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
194 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
200 return decodeUImmOperand<3>(Inst, Imm); in decodeU3ImmOperand()
206 return decodeUImmOperand<4>(Inst, Imm); in decodeU4ImmOperand()
212 return decodeUImmOperand<6>(Inst, Imm); in decodeU6ImmOperand()
218 return decodeUImmOperand<8>(Inst, Imm); in decodeU8ImmOperand()
224 return decodeUImmOperand<12>(Inst, Imm); in decodeU12ImmOperand()
230 return decodeUImmOperand<16>(Inst, Imm); in decodeU16ImmOperand()
242 return decodeSImmOperand<8>(Inst, Imm); in decodeS8ImmOperand()
484 uint64_t Inst = 0; in getInstruction() local
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp641 Inst.addOperand( in DecodeMatrixTile()
760 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4)) in DecodePCRelLabel19()
901 switch (Inst.getOpcode()) { in DecodeThreeAddrSRegInstruction()
961 switch (Inst.getOpcode()) { in DecodeMoveImmInstruction()
980 Inst.addOperand(Inst.getOperand(0)); in DecodeMoveImmInstruction()
994 switch (Inst.getOpcode()) { in DecodeUnsignedLdStInstruction()
1059 switch (Inst.getOpcode()) { in DecodeSignedLdStInstruction()
1112 switch (Inst.getOpcode()) { in DecodeSignedLdStInstruction()
1470 switch (Inst.getOpcode()) { in DecodeAuthLoadInstruction()
1506 switch (Inst.getOpcode()) { in DecodeAddSubERegInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td13 let Inst{15} = 0;
14 let Inst{14 - 10} = sop;
22 let Inst{15} = 0;
34 let Inst{10 - 8} = rx;
35 let Inst{7 - 5} = rz;
36 let Inst{4 - 2} = ry;
37 let Inst{1, 0} = sop;
47 let Inst{9 - 6} = rz;
48 let Inst{5 - 2} = rx;
49 let Inst{1, 0} = sop;
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H A DCSKYInstrFormats.td45 field bits<32> Inst;
51 field bits<16> Inst;
138 let Inst{15 - 0} = 0;
151 let Inst{15 - 2} = 0;
161 let Inst{15 - 0} = 0;
318 let Inst{4 - 0} = 0;
319 let Inst{25} = S;
320 let Inst{21} = I;
331 let Inst{4 - 0} = 0;
350 let Inst{15} = 1;
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td15 field bits<32> Inst;
22 let Inst{0-5} = opcode;
80 field bits<64> Inst;
232 let Inst{6-10} = A;
582 let Inst{6} = 0;
587 let Inst{31} = 0;
628 let Inst{15} = L;
1690 let Inst{6} = 0;
1692 let Inst{15} = 0;
2137 let Inst{15} = R;
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget()
106 return decodeRegisterClass(Inst, RegNo, FRegs); in DecodeF4RCRegisterClass()
204 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
222 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand()
246 switch (Inst.getOpcode()) { in decodeMemRIOperands()
262 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
282 if (Inst.getOpcode() == PPC::LDU) in decodeMemRIXOperands()
285 else if (Inst.getOpcode() == PPC::STDU) in decodeMemRIXOperands()
286 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
305 Inst.addOperand(MCOperand::createImm(Disp)); in decodeMemRIHashOperands()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td62 let Inst{31} = 1;
63 let Inst{30} = 1;
67 let Inst{11-7} = rd;
79 let Inst{31} = 0;
95 let Inst{31} = 1;
115 let Inst{25} = vm;
135 let Inst{25} = vm;
154 let Inst{25} = vm;
174 let Inst{25} = vm;
193 let Inst{25} = vm;
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/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1742 switch (Inst.getOpcode()) { in DecodeRegListOperand()
1875 switch (Inst.getOpcode()) { in DecodeCopMemInstruction()
1952 switch (Inst.getOpcode()) { in DecodeCopMemInstruction()
2013 switch (Inst.getOpcode()) { in DecodeCopMemInstruction()
2055 switch (Inst.getOpcode()) { in DecodeAddrMode2IdxInstruction()
2193 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) in DecodeTSBInstruction()
2521 Inst.addOperand( in DecodeMemMultipleWritebackInstruction()
2673 Inst.setOpcode(Opcode); in DecodeT2HintSpaceInstruction()
3038 switch(Inst.getOpcode()) { in DecodeVLDInstruction()
3944 switch(Inst.getOpcode()) { in DecodeThumbAddSpecialReg()
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/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp137 if (!isCall(Inst)) in getEHInfo()
153 if (isCall(Inst)) { in addEHInfo()
163 if (!isInvoke(Inst)) in updateEHInfo()
300 Inst.erase(std::prev(Inst.end())); in stripAnnotations()
330 if (isPrefix(Inst) || isCFI(Inst)) in getClobberedRegs()
347 if (isPrefix(Inst) || isCFI(Inst)) in getTouchedRegs()
367 if (isPrefix(Inst) || isCFI(Inst)) in getWrittenRegs()
384 if (isPrefix(Inst) || isCFI(Inst)) in getUsedRegs()
401 if (isPrefix(Inst) || isCFI(Inst)) in getSrcRegs()
417 if (isRep(Inst)) in getSrcRegs()
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/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td22 field bits<32> Inst;
54 let Inst{9-5} = rj;
55 let Inst{4-0} = rd;
69 let Inst{9-5} = rj;
70 let Inst{4-0} = rd;
86 let Inst{9-5} = rj;
87 let Inst{4-0} = rd;
103 let Inst{9-5} = rj;
104 let Inst{4-0} = rd;
118 let Inst{9-5} = rj;
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/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrFormats.td14 field bits<64> Inst;
162 let Inst{5} = N;
181 let Inst{4} = 0;
203 let Inst{17} = 1;
211 let Inst{17} = 0;
232 let Inst{16} = 1;
236 let Inst{5} = N;
238 let Inst{3} = 0;
305 let Inst{5} = 0;
349 let Inst{5} = 1;
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
265 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP || in addImplySP()
266 Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP || in addImplySP()
267 Inst.getOpcode() == RISCV::C_FLWSP || in addImplySP()
268 Inst.getOpcode() == RISCV::C_FSWSP || in addImplySP()
285 addImplySP(Inst, Address, Decoder); in decodeUImmOperand()
304 addImplySP(Inst, Address, Decoder); in decodeSImmOperand()
401 Inst.addOperand(Inst.getOperand(0)); in decodeRVCInstrRdRs1UImm()
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/llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp163 Inst.addOperand(MCOperand::createImm(b)); in decodeFIOBIT()
233 Inst.addOperand(MCOperand::createImm(k)); in decodeFWRdK()
260 Inst.addOperand( in decodeMemri()
279 Inst.setOpcode(AVR::LDDRdPtrQ); in decodeLoadStore()
284 Inst.setOpcode(AVR::STDPtrQRr); in decodeLoadStore()
332 Inst.setOpcode(AVR::STPtrRr); in decodeLoadStore()
337 Inst.setOpcode(AVR::STPtrPiRr); in decodeLoadStore()
340 Inst.setOpcode(AVR::STPtrPdRr); in decodeLoadStore()
343 Inst.setOpcode(AVR::LDRdPtr); in decodeLoadStore()
348 Inst.setOpcode(AVR::LDRdPtrPi); in decodeLoadStore()
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/llvm-project-15.0.7/bolt/include/bolt/Core/
H A DMCPlusBuilder.h100 if (Inst.getNumOperands() == 0) in getAnnotationInst()
103 const MCOperand &LastOp = Inst.getOperand(Inst.getNumOperands() - 1); in getAnnotationInst()
164 void setTailCall(MCInst &Inst);
352 return Analysis->isBranch(Inst); in isBranch()
366 return Analysis->isUnconditionalBranch(Inst) && !isTailCall(Inst); in isUnconditionalBranch()
454 return Analysis->isCall(Inst) || isTailCall(Inst); in isCall()
884 return Inst.end(); in getMemOperandDisp()
1036 return isCall(Inst) && getEHInfo(Inst); in isInvoke()
1100 bool clearOffset(MCInst &Inst);
1549 Inst.clear(); in createCFI()
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