Lines Matching refs:Inst
58 bool isADRP(const MCInst &Inst) const override { in isADRP()
59 return Inst.getOpcode() == AArch64::ADRP; in isADRP()
62 bool isADR(const MCInst &Inst) const override { in isADR()
63 return Inst.getOpcode() == AArch64::ADR; in isADR()
66 void getADRReg(const MCInst &Inst, MCPhysReg &RegName) const override { in getADRReg() argument
67 assert((isADR(Inst) || isADRP(Inst)) && "Not an ADR instruction"); in getADRReg()
68 assert(MCPlus::getNumPrimeOperands(Inst) != 0 && in getADRReg()
70 assert(Inst.getOperand(0).isReg() && in getADRReg()
72 RegName = Inst.getOperand(0).getReg(); in getADRReg()
75 bool isTB(const MCInst &Inst) const { in isTB()
76 return (Inst.getOpcode() == AArch64::TBNZW || in isTB()
77 Inst.getOpcode() == AArch64::TBNZX || in isTB()
78 Inst.getOpcode() == AArch64::TBZW || in isTB()
79 Inst.getOpcode() == AArch64::TBZX); in isTB()
82 bool isCB(const MCInst &Inst) const { in isCB()
83 return (Inst.getOpcode() == AArch64::CBNZW || in isCB()
84 Inst.getOpcode() == AArch64::CBNZX || in isCB()
85 Inst.getOpcode() == AArch64::CBZW || in isCB()
86 Inst.getOpcode() == AArch64::CBZX); in isCB()
89 bool isMOVW(const MCInst &Inst) const { in isMOVW()
90 return (Inst.getOpcode() == AArch64::MOVKWi || in isMOVW()
91 Inst.getOpcode() == AArch64::MOVKXi || in isMOVW()
92 Inst.getOpcode() == AArch64::MOVNWi || in isMOVW()
93 Inst.getOpcode() == AArch64::MOVNXi || in isMOVW()
94 Inst.getOpcode() == AArch64::MOVZXi || in isMOVW()
95 Inst.getOpcode() == AArch64::MOVZWi); in isMOVW()
98 bool isADD(const MCInst &Inst) const { in isADD()
99 return (Inst.getOpcode() == AArch64::ADDSWri || in isADD()
100 Inst.getOpcode() == AArch64::ADDSWrr || in isADD()
101 Inst.getOpcode() == AArch64::ADDSWrs || in isADD()
102 Inst.getOpcode() == AArch64::ADDSWrx || in isADD()
103 Inst.getOpcode() == AArch64::ADDSXri || in isADD()
104 Inst.getOpcode() == AArch64::ADDSXrr || in isADD()
105 Inst.getOpcode() == AArch64::ADDSXrs || in isADD()
106 Inst.getOpcode() == AArch64::ADDSXrx || in isADD()
107 Inst.getOpcode() == AArch64::ADDSXrx64 || in isADD()
108 Inst.getOpcode() == AArch64::ADDWri || in isADD()
109 Inst.getOpcode() == AArch64::ADDWrr || in isADD()
110 Inst.getOpcode() == AArch64::ADDWrs || in isADD()
111 Inst.getOpcode() == AArch64::ADDWrx || in isADD()
112 Inst.getOpcode() == AArch64::ADDXri || in isADD()
113 Inst.getOpcode() == AArch64::ADDXrr || in isADD()
114 Inst.getOpcode() == AArch64::ADDXrs || in isADD()
115 Inst.getOpcode() == AArch64::ADDXrx || in isADD()
116 Inst.getOpcode() == AArch64::ADDXrx64); in isADD()
119 bool isLDRB(const MCInst &Inst) const { in isLDRB()
120 return (Inst.getOpcode() == AArch64::LDRBBpost || in isLDRB()
121 Inst.getOpcode() == AArch64::LDRBBpre || in isLDRB()
122 Inst.getOpcode() == AArch64::LDRBBroW || in isLDRB()
123 Inst.getOpcode() == AArch64::LDRBBroX || in isLDRB()
124 Inst.getOpcode() == AArch64::LDRBBui || in isLDRB()
125 Inst.getOpcode() == AArch64::LDRSBWpost || in isLDRB()
126 Inst.getOpcode() == AArch64::LDRSBWpre || in isLDRB()
127 Inst.getOpcode() == AArch64::LDRSBWroW || in isLDRB()
128 Inst.getOpcode() == AArch64::LDRSBWroX || in isLDRB()
129 Inst.getOpcode() == AArch64::LDRSBWui || in isLDRB()
130 Inst.getOpcode() == AArch64::LDRSBXpost || in isLDRB()
131 Inst.getOpcode() == AArch64::LDRSBXpre || in isLDRB()
132 Inst.getOpcode() == AArch64::LDRSBXroW || in isLDRB()
133 Inst.getOpcode() == AArch64::LDRSBXroX || in isLDRB()
134 Inst.getOpcode() == AArch64::LDRSBXui); in isLDRB()
137 bool isLDRH(const MCInst &Inst) const { in isLDRH()
138 return (Inst.getOpcode() == AArch64::LDRHHpost || in isLDRH()
139 Inst.getOpcode() == AArch64::LDRHHpre || in isLDRH()
140 Inst.getOpcode() == AArch64::LDRHHroW || in isLDRH()
141 Inst.getOpcode() == AArch64::LDRHHroX || in isLDRH()
142 Inst.getOpcode() == AArch64::LDRHHui || in isLDRH()
143 Inst.getOpcode() == AArch64::LDRSHWpost || in isLDRH()
144 Inst.getOpcode() == AArch64::LDRSHWpre || in isLDRH()
145 Inst.getOpcode() == AArch64::LDRSHWroW || in isLDRH()
146 Inst.getOpcode() == AArch64::LDRSHWroX || in isLDRH()
147 Inst.getOpcode() == AArch64::LDRSHWui || in isLDRH()
148 Inst.getOpcode() == AArch64::LDRSHXpost || in isLDRH()
149 Inst.getOpcode() == AArch64::LDRSHXpre || in isLDRH()
150 Inst.getOpcode() == AArch64::LDRSHXroW || in isLDRH()
151 Inst.getOpcode() == AArch64::LDRSHXroX || in isLDRH()
152 Inst.getOpcode() == AArch64::LDRSHXui); in isLDRH()
155 bool isLDRW(const MCInst &Inst) const { in isLDRW()
156 return (Inst.getOpcode() == AArch64::LDRWpost || in isLDRW()
157 Inst.getOpcode() == AArch64::LDRWpre || in isLDRW()
158 Inst.getOpcode() == AArch64::LDRWroW || in isLDRW()
159 Inst.getOpcode() == AArch64::LDRWroX || in isLDRW()
160 Inst.getOpcode() == AArch64::LDRWui); in isLDRW()
163 bool isLDRX(const MCInst &Inst) const { in isLDRX()
164 return (Inst.getOpcode() == AArch64::LDRXpost || in isLDRX()
165 Inst.getOpcode() == AArch64::LDRXpre || in isLDRX()
166 Inst.getOpcode() == AArch64::LDRXroW || in isLDRX()
167 Inst.getOpcode() == AArch64::LDRXroX || in isLDRX()
168 Inst.getOpcode() == AArch64::LDRXui); in isLDRX()
171 bool isLoad(const MCInst &Inst) const override { in isLoad()
172 return isLDRB(Inst) || isLDRH(Inst) || isLDRW(Inst) || isLDRX(Inst); in isLoad()
175 bool isLoadFromStack(const MCInst &Inst) const { in isLoadFromStack()
176 if (!isLoad(Inst)) in isLoadFromStack()
178 const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); in isLoadFromStack()
181 const MCOperand &Operand = Inst.getOperand(I); in isLoadFromStack()
192 bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From, in isRegToRegMove() argument
194 if (Inst.getOpcode() != AArch64::ORRXrs) in isRegToRegMove()
196 if (Inst.getOperand(1).getReg() != AArch64::XZR) in isRegToRegMove()
198 if (Inst.getOperand(3).getImm() != 0) in isRegToRegMove()
200 From = Inst.getOperand(2).getReg(); in isRegToRegMove()
201 To = Inst.getOperand(0).getReg(); in isRegToRegMove()
205 bool isIndirectCall(const MCInst &Inst) const override { in isIndirectCall()
206 return Inst.getOpcode() == AArch64::BLR; in isIndirectCall()
209 bool hasPCRelOperand(const MCInst &Inst) const override { in hasPCRelOperand()
213 if (isADRP(Inst)) in hasPCRelOperand()
216 if (isADR(Inst)) in hasPCRelOperand()
220 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); in hasPCRelOperand()
228 bool evaluateADR(const MCInst &Inst, int64_t &Imm, in evaluateADR() argument
230 assert((isADR(Inst) || isADRP(Inst)) && "Not an ADR instruction"); in evaluateADR()
232 const MCOperand &Label = Inst.getOperand(1); in evaluateADR()
240 if (Inst.getOpcode() == AArch64::ADR) { in evaluateADR()
248 bool evaluateAArch64MemoryOperand(const MCInst &Inst, int64_t &DispImm, in evaluateAArch64MemoryOperand() argument
250 if (isADR(Inst) || isADRP(Inst)) in evaluateAArch64MemoryOperand()
251 return evaluateADR(Inst, DispImm, DispExpr); in evaluateAArch64MemoryOperand()
254 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); in evaluateAArch64MemoryOperand()
259 if (!Inst.getOperand(I).isImm()) { in evaluateAArch64MemoryOperand()
260 assert(Inst.getOperand(I).isExpr() && "Unexpected PCREL operand"); in evaluateAArch64MemoryOperand()
262 *DispExpr = Inst.getOperand(I).getExpr(); in evaluateAArch64MemoryOperand()
266 DispImm = Inst.getOperand(I).getImm() << 2; in evaluateAArch64MemoryOperand()
272 bool evaluateMemOperandTarget(const MCInst &Inst, uint64_t &Target, in evaluateMemOperandTarget() argument
277 if (!evaluateAArch64MemoryOperand(Inst, DispValue, &DispExpr)) in evaluateMemOperandTarget()
285 if (Inst.getOpcode() == AArch64::ADRP) in evaluateMemOperandTarget()
292 bool replaceMemOperandDisp(MCInst &Inst, MCOperand Operand) const override { in replaceMemOperandDisp() argument
293 MCInst::iterator OI = Inst.begin(); in replaceMemOperandDisp()
294 if (isADR(Inst) || isADRP(Inst)) { in replaceMemOperandDisp()
295 assert(MCPlus::getNumPrimeOperands(Inst) >= 2 && in replaceMemOperandDisp()
299 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); in replaceMemOperandDisp()
305 assert(OI != Inst.end() && "Literal operand not found"); in replaceMemOperandDisp()
311 const MCExpr *getTargetExprFor(MCInst &Inst, const MCExpr *Expr, in getTargetExprFor() argument
315 if (isADR(Inst) || RelType == ELF::R_AARCH64_ADR_PREL_LO21 || in getTargetExprFor()
318 } else if (isADRP(Inst) || RelType == ELF::R_AARCH64_ADR_PREL_PG_HI21 || in getTargetExprFor()
358 bool getSymbolRefOperandNum(const MCInst &Inst, unsigned &OpNum) const { in getSymbolRefOperandNum() argument
359 if (OpNum >= MCPlus::getNumPrimeOperands(Inst)) in getSymbolRefOperandNum()
364 if (isConditionalBranch(Inst) || isADR(Inst) || isADRP(Inst)) in getSymbolRefOperandNum()
366 if (isTB(Inst)) in getSymbolRefOperandNum()
368 if (isMOVW(Inst)) in getSymbolRefOperandNum()
391 const MCSymbol *getTargetSymbol(const MCInst &Inst, in getTargetSymbol() argument
393 if (!getSymbolRefOperandNum(Inst, OpNum)) in getTargetSymbol()
396 const MCOperand &Op = Inst.getOperand(OpNum); in getTargetSymbol()
419 int64_t getTargetAddend(const MCInst &Inst, in getTargetAddend() argument
421 if (!getSymbolRefOperandNum(Inst, OpNum)) in getTargetAddend()
424 const MCOperand &Op = Inst.getOperand(OpNum); in getTargetAddend()
431 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, in evaluateBranch() argument
435 if (isConditionalBranch(Inst)) { in evaluateBranch()
436 assert(MCPlus::getNumPrimeOperands(Inst) >= 2 && in evaluateBranch()
441 if (isTB(Inst)) { in evaluateBranch()
442 assert(MCPlus::getNumPrimeOperands(Inst) >= 3 && in evaluateBranch()
447 if (Info->get(Inst.getOpcode()).OpInfo[OpNum].OperandType != in evaluateBranch()
449 assert((isIndirectBranch(Inst) || isIndirectCall(Inst)) && in evaluateBranch()
454 int64_t Imm = Inst.getOperand(OpNum).getImm() << 2; in evaluateBranch()
459 bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB, in replaceBranchTarget() argument
461 assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) && in replaceBranchTarget()
463 assert(MCPlus::getNumPrimeOperands(Inst) >= 1 && in replaceBranchTarget()
465 MCInst::iterator OI = Inst.begin(); in replaceBranchTarget()
467 if (isConditionalBranch(Inst)) { in replaceBranchTarget()
468 assert(MCPlus::getNumPrimeOperands(Inst) >= 2 && in replaceBranchTarget()
473 if (isTB(Inst)) { in replaceBranchTarget()
474 assert(MCPlus::getNumPrimeOperands(Inst) >= 3 && in replaceBranchTarget()
476 OI = Inst.begin() + 2; in replaceBranchTarget()
498 const MCInst &Inst, in analyzeIndirectBranchFragment() argument
503 assert(Inst.getOpcode() == AArch64::BR && "Unexpected opcode"); in analyzeIndirectBranchFragment()
506 SmallVector<MCInst *, 4> &UsesRoot = UDChain[&Inst]; in analyzeIndirectBranchFragment()
787 unsigned getCondCode(const MCInst &Inst) const override { in getCondCode()
790 return Inst.getOpcode(); in getCondCode()
804 bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB, in reverseBranchCondition() argument
806 if (isTB(Inst) || isCB(Inst)) { in reverseBranchCondition()
807 Inst.setOpcode(getInvertedBranchOpcode(Inst.getOpcode())); in reverseBranchCondition()
808 assert(Inst.getOpcode() != 0 && "Invalid branch instruction"); in reverseBranchCondition()
809 } else if (Inst.getOpcode() == AArch64::Bcc) { in reverseBranchCondition()
810 Inst.getOperand(0).setImm(AArch64CC::getInvertedCondCode( in reverseBranchCondition()
811 static_cast<AArch64CC::CondCode>(Inst.getOperand(0).getImm()))); in reverseBranchCondition()
812 assert(Inst.getOperand(0).getImm() != AArch64CC::AL && in reverseBranchCondition()
813 Inst.getOperand(0).getImm() != AArch64CC::NV && in reverseBranchCondition()
816 LLVM_DEBUG(Inst.dump()); in reverseBranchCondition()
819 return replaceBranchTarget(Inst, TBB, Ctx); in reverseBranchCondition()
822 int getPCRelEncodingSize(const MCInst &Inst) const override { in getPCRelEncodingSize()
823 switch (Inst.getOpcode()) { in getPCRelEncodingSize()
845 bool createTailCall(MCInst &Inst, const MCSymbol *Target, in createTailCall() argument
847 Inst.setOpcode(AArch64::B); in createTailCall()
848 Inst.addOperand(MCOperand::createExpr(getTargetExprFor( in createTailCall()
849 Inst, MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx), in createTailCall()
851 setTailCall(Inst); in createTailCall()
860 bool createTrap(MCInst &Inst) const override { in createTrap()
861 Inst.clear(); in createTrap()
862 Inst.setOpcode(AArch64::BRK); in createTrap()
863 Inst.addOperand(MCOperand::createImm(1)); in createTrap()
867 bool convertJmpToTailCall(MCInst &Inst) override { in convertJmpToTailCall() argument
868 setTailCall(Inst); in convertJmpToTailCall()
872 bool convertTailCallToJmp(MCInst &Inst) override { in convertTailCallToJmp() argument
873 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); in convertTailCallToJmp()
874 clearOffset(Inst); in convertTailCallToJmp()
875 if (getConditionalTailCall(Inst)) in convertTailCallToJmp()
876 unsetConditionalTailCall(Inst); in convertTailCallToJmp()
880 bool lowerTailCall(MCInst &Inst) override { in lowerTailCall() argument
881 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); in lowerTailCall()
882 if (getConditionalTailCall(Inst)) in lowerTailCall()
883 unsetConditionalTailCall(Inst); in lowerTailCall()
887 bool isNoop(const MCInst &Inst) const override { in isNoop()
888 return Inst.getOpcode() == AArch64::HINT && in isNoop()
889 Inst.getOperand(0).getImm() == 0; in isNoop()
892 bool createNoop(MCInst &Inst) const override { in createNoop()
893 Inst.setOpcode(AArch64::HINT); in createNoop()
894 Inst.clear(); in createNoop()
895 Inst.addOperand(MCOperand::createImm(0)); in createNoop()
899 bool isStore(const MCInst &Inst) const override { return false; } in isStore()
962 MCInst Inst; in createLongJmp() local
963 Inst.setOpcode(AArch64::MOVZXi); in createLongJmp()
964 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
965 Inst.addOperand(MCOperand::createExpr(AArch64MCExpr::create( in createLongJmp()
968 Inst.addOperand(MCOperand::createImm(0x30)); in createLongJmp()
969 Seq.emplace_back(Inst); in createLongJmp()
971 Inst.clear(); in createLongJmp()
972 Inst.setOpcode(AArch64::MOVKXi); in createLongJmp()
973 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
974 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
975 Inst.addOperand(MCOperand::createExpr(AArch64MCExpr::create( in createLongJmp()
978 Inst.addOperand(MCOperand::createImm(0x20)); in createLongJmp()
979 Seq.emplace_back(Inst); in createLongJmp()
981 Inst.clear(); in createLongJmp()
982 Inst.setOpcode(AArch64::MOVKXi); in createLongJmp()
983 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
984 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
985 Inst.addOperand(MCOperand::createExpr(AArch64MCExpr::create( in createLongJmp()
988 Inst.addOperand(MCOperand::createImm(0x10)); in createLongJmp()
989 Seq.emplace_back(Inst); in createLongJmp()
991 Inst.clear(); in createLongJmp()
992 Inst.setOpcode(AArch64::MOVKXi); in createLongJmp()
993 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
994 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
995 Inst.addOperand(MCOperand::createExpr(AArch64MCExpr::create( in createLongJmp()
998 Inst.addOperand(MCOperand::createImm(0)); in createLongJmp()
999 Seq.emplace_back(Inst); in createLongJmp()
1001 Inst.clear(); in createLongJmp()
1002 Inst.setOpcode(AArch64::BR); in createLongJmp()
1003 Inst.addOperand(MCOperand::createReg(AArch64::X16)); in createLongJmp()
1005 setTailCall(Inst); in createLongJmp()
1006 Seq.emplace_back(Inst); in createLongJmp()
1020 MCInst &Inst = Insts.back(); in createShortJmp() local
1021 Inst.clear(); in createShortJmp()
1022 Inst.setOpcode(AArch64::BR); in createShortJmp()
1023 Inst.addOperand(MCOperand::createReg(Reg)); in createShortJmp()
1025 setTailCall(Inst); in createShortJmp()
1071 bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol, in replaceImmWithSymbolRef() argument
1075 for (unsigned Index = 0; Index < MCPlus::getNumPrimeOperands(Inst); in replaceImmWithSymbolRef()
1077 if (Inst.getOperand(Index).isImm()) { in replaceImmWithSymbolRef()
1085 Value = Inst.getOperand(ImmOpNo).getImm(); in replaceImmWithSymbolRef()
1087 setOperandToSymbolRef(Inst, ImmOpNo, Symbol, Addend, Ctx, RelType); in replaceImmWithSymbolRef()
1092 bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB, in createUncondBranch() argument
1094 Inst.setOpcode(AArch64::B); in createUncondBranch()
1095 Inst.clear(); in createUncondBranch()
1096 Inst.addOperand(MCOperand::createExpr(getTargetExprFor( in createUncondBranch()
1097 Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx), in createUncondBranch()
1102 bool isMoveMem2Reg(const MCInst &Inst) const override { return false; } in isMoveMem2Reg()
1104 bool isLeave(const MCInst &Inst) const override { return false; } in isLeave()
1106 bool isPop(const MCInst &Inst) const override { return false; } in isPop()
1108 bool isPrefix(const MCInst &Inst) const override { return false; } in isPrefix()
1110 bool createReturn(MCInst &Inst) const override { in createReturn()
1111 Inst.setOpcode(AArch64::RET); in createReturn()
1112 Inst.clear(); in createReturn()
1113 Inst.addOperand(MCOperand::createReg(AArch64::LR)); in createReturn()