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Searched refs:ImplicitDefs (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h207 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
587 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
591 if (!ImplicitDefs) in getNumImplicitDefs()
594 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DParallelSnippetGenerator.cpp194 BitVector ImplicitDefs(State.getRegInfo().getNumRegs()); in generateCodeTemplates() local
202 ImplicitDefs.set(Op.getImplicitReg()); in generateCodeTemplates()
209 getAliasedBits(State.getRegInfo(), ImplicitDefs); in generateCodeTemplates()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegReAssign.cpp159 const MCPhysReg *ImplicitDefs = Desc.getImplicitDefs(); in rankRegisters() local
160 while (ImplicitDefs && *ImplicitDefs) { in rankRegisters()
162 BC.MIB->getAliases(*ImplicitDefs, false).find_first(); in rankRegisters()
165 ++ImplicitDefs; in rankRegisters()
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp335 const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); in getClobberedRegs() local
337 Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false); in getClobberedRegs()
352 const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); in getTouchedRegs() local
354 Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false); in getTouchedRegs()
372 const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); in getWrittenRegs() local
374 Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true); in getWrittenRegs()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DInstrDocsEmitter.cpp189 if (!II->ImplicitDefs.empty()) { in EmitInstrDocs()
192 for (Record *Def : II->ImplicitDefs) in EmitInstrDocs()
H A DCodeGenInstruction.cpp419 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
454 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
457 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
H A DCodeGenInstruction.h234 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
H A DDAGISelMatcherGen.cpp926 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
1068 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
H A DGlobalISelEmitter.cpp3137 if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) { in emitActionOpcodes()
3138 for (auto Def : I->ImplicitDefs) { in emitActionOpcodes()
3654 const std::vector<Record *> &ImplicitDefs) const;
5017 const std::vector<Record *> &ImplicitDefs) const { in importImplicitDefRenderers()
5018 if (!ImplicitDefs.empty()) in importImplicitDefRenderers()
H A DCodeGenDAGPatterns.cpp2586 if (!InstInfo.ImplicitDefs.empty()) { in ApplyTypeConstraints()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineCSE.cpp520 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlockCSE() local
628 ImplicitDefs.push_back(OldReg); in ProcessBlockCSE()
693 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
700 for (auto ImplicitDef : ImplicitDefs) in ProcessBlockCSE()
728 ImplicitDefs.clear(); in ProcessBlockCSE()
H A DMachineInstr.cpp88 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCInstrDesc.cpp34 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1940 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
1964 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
1990 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
2012 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
2036 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
2055 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
2080 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
2096 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
H A DScheduleDAGFast.cpp429 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
529 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
H A DScheduleDAGRRList.cpp1284 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1438 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp163 if (const MCPhysReg *R = D.ImplicitDefs) in getDefsUses()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp313 .addReg(II.ImplicitDefs[0])); in fastEmitInst_r()
340 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rr()
365 .addReg(II.ImplicitDefs[0])); in fastEmitInst_ri()
384 .addReg(II.ImplicitDefs[0])); in fastEmitInst_i()
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp1362 if (MCID.ImplicitDefs) in verifyImplicitOperands()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp4001 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrrr()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2736 if (NewDesc.ImplicitDefs) in optimizeCompareInstr()
/llvm-project-15.0.7/llvm/docs/
H A DCodeGenerator.rst1353 ``TargetInstrInfo::get(opcode)::ImplicitDefs``, where ``opcode`` is the opcode