| /llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/ |
| H A D | ReduceRegisterDefs.cpp | 98 unsigned ImpDef = IsGeneric ? TargetOpcode::G_IMPLICIT_DEF in removeDefsFromFunction() local
102 InsPt = BuildMI(MBB, InsPt, DebugLoc(), TII->get(ImpDef)) in removeDefsFromFunction()
|
| H A D | ReduceInstructionsMIR.cpp | 129 unsigned ImpDef = IsGeneric ? TargetOpcode::G_IMPLICIT_DEF in extractInstrFromFunction() local
131 BuildMI(*EntryMBB, EntryInsPt, DebugLoc(), TII->get(ImpDef)) in extractInstrFromFunction()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 109 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) in init() local
110 for (; *ImpDef; ++ImpDef) { in init()
111 unsigned R = *ImpDef; in init()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGFast.cpp | 431 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT() local
432 if (Reg == *ImpDef) in getPhysicalRegisterVT()
|
| H A D | ScheduleDAGRRList.cpp | 1286 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT() local
1287 if (Reg == *ImpDef) in getPhysicalRegisterVT()
2875 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef) in canClobberReachingPhysRegUse() local
2879 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 333 MachineInstrBuilder ImpDef = BuildMI(*PredMBB, InsertPos, in computeMainRangesFixFlags() local
335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | fix-sgpr-copies.mir | 64 # Avoid infinite loop in SIInstrInfo::legalizeGenericOperand when checking for ImpDef.
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 3509 if (const MCPhysReg *ImpDef = MI.getDesc().getImplicitDefs()) { in modifiesModeRegister() local
3510 for (; ImpDef && *ImpDef; ++ImpDef) { in modifiesModeRegister()
3511 if (*ImpDef == AMDGPU::MODE) in modifiesModeRegister()
5458 bool ImpDef = Def->isImplicitDef(); in legalizeGenericOperand() local
5459 while (!ImpDef && Def && Def->isCopy()) { in legalizeGenericOperand()
5463 ImpDef = Def && Def->isImplicitDef(); in legalizeGenericOperand()
5466 !ImpDef) in legalizeGenericOperand()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 492 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectBuildVector() local
497 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0); in SelectBuildVector()
|
| H A D | SIISelLowering.cpp | 11823 SDValue ImpDef = DAG.getCopyToReg(DAG.getEntryNode(), SDLoc(Node), in PostISelFolding() local
11848 Ops.push_back(ImpDef.getValue(1)); in PostISelFolding()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 959 for (unsigned ImpDef : ImpDefs) in MergeOpsUpdate() local
960 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1097 SDValue ImpDef = SDValue( in Widen() local
1100 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg); in Widen()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1173 MachineInstr *ImpDef = in convertToThreeAddressWithLEA() local
1260 LIS->InsertMachineInstrInMaps(*ImpDef); in convertToThreeAddressWithLEA()
|