| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 23 #ifndef INSTRUCTION
24 #define INSTRUCTION(N,A,R,I)
27 // DAG_INSTRUCTION is treated like an INSTRUCTION if the DAG node isn't used.
29 #define DAG_INSTRUCTION(N,A,R,I,D) INSTRUCTION(N,A,R,I)
34 #define FUNCTION(N,A,R,I) INSTRUCTION(N,A,R,I)
103 #undef INSTRUCTION
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| /llvm-project-15.0.7/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX1011.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
51 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS…
61 **INSTRUCTION** **DST** **SRC0** **SRC1**
71 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX906.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
54 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
64 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIF…
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| H A D | AMDGPUAsmGFX908.rst | 41 **INSTRUCTION** **SRC0** **SRC1** **SRC2** **MODIFIERS**
51 …**INSTRUCTION** **SRC0** **SRC1** **SRC2** **SRC3** **…
61 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
83 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
93 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
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| H A D | AMDGPUAsmGFX1013.rst | 41 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
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| H A D | AMDGPUAsmGFX904.rst | 41 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MO…
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| H A D | AMDGPUAsmGFX900.rst | 41 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MO…
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| H A D | AMDGPUAsmGFX7.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
193 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIER…
427 **INSTRUCTION** **DST** **SRC0** **SRC1**
448 **INSTRUCTION** **DST** **SRC**
504 **INSTRUCTION** **DST** **SRC0** **SRC1**
555 **INSTRUCTION** **SRC0** **SRC1**
580 **INSTRUCTION** **DST** **SRC0** **SRC1**
608 **INSTRUCTION** **SRC**
642 **INSTRUCTION** **DST** **SRC0** **SRC1**
653 **INSTRUCTION** **DST** **SRC**
[all …]
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| H A D | AMDGPUAsmGFX10.rst | 39 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **…
562 **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
1102 **INSTRUCTION** **DST** **SRC**
1175 **INSTRUCTION** **DST** **SRC0** **SRC1**
1234 **INSTRUCTION** **SRC0** **SRC1**
1260 **INSTRUCTION** **DST** **SRC0** **SRC1**
1295 **INSTRUCTION** **SRC**
1340 **INSTRUCTION** **DST** **SRC0** **SRC1**
1351 **INSTRUCTION** **DST** **SRC**
1931 … **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
[all …]
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| H A D | AMDGPUAsmGFX1030.rst | 41 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **…
538 **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
990 **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
1012 **INSTRUCTION** **DST** **SRC**
1085 **INSTRUCTION** **DST** **SRC0** **SRC1**
1144 **INSTRUCTION** **SRC0** **SRC1**
1170 **INSTRUCTION** **DST** **SRC0** **SRC1**
1205 **INSTRUCTION** **SRC**
1249 **INSTRUCTION** **DST** **SRC0** **SRC1**
1260 **INSTRUCTION** **DST** **SRC**
[all …]
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| H A D | AMDGPUAsmGFX8.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
200 …**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIER…
248 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFI…
468 **INSTRUCTION** **DST** **SRC**
525 **INSTRUCTION** **DST** **SRC0** **SRC1**
577 **INSTRUCTION** **SRC0** **SRC1**
605 **INSTRUCTION** **DST** **SRC0** **SRC1**
633 **INSTRUCTION** **SRC**
671 **INSTRUCTION** **DST** **SRC0** **SRC1**
682 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
[all …]
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| H A D | AMDGPUAsmGFX9.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
336 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
626 **INSTRUCTION** **DST** **SRC**
688 **INSTRUCTION** **DST** **SRC0** **SRC1**
749 **INSTRUCTION** **SRC0** **SRC1**
777 **INSTRUCTION** **DST** **SRC0** **SRC1**
806 **INSTRUCTION** **SRC**
845 **INSTRUCTION** **DST** **SRC0** **SRC1**
856 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
1664 … **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
[all …]
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| H A D | AMDGPUAsmGFX90a.rst | 39 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** …
305 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFI…
338 …**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MO…
538 **INSTRUCTION** **DST** **SRC**
600 **INSTRUCTION** **DST** **SRC0** **SRC1**
661 **INSTRUCTION** **SRC0** **SRC1**
689 **INSTRUCTION** **DST** **SRC0** **SRC1**
718 **INSTRUCTION** **SRC**
757 **INSTRUCTION** **DST** **SRC** **MODIFIERS**
969 …**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIF…
[all …]
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | FPEnv.cpp | 99 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in getConstrainedIntrinsicID() macro
115 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) in getConstrainedIntrinsicID() macro
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| H A D | IntrinsicInst.cpp | 302 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isUnaryOp() macro
313 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isTernaryOp() macro
322 #define INSTRUCTION(NAME, NARGS, ROUND_MODE, INTRINSIC) \ in classof() macro
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| H A D | IRBuilder.cpp | 946 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in CreateConstrainedFPCast() macro
1005 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in CreateConstrainedFPCall() macro
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| H A D | Function.cpp | 448 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in isConstrainedFPIntrinsic() macro
452 #undef INSTRUCTION in isConstrainedFPIntrinsic()
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| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ |
| H A D | first-order-recurrence-sink-replicate-region.ll | 42 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%lv>
62 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%rem>
137 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
206 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
282 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv>
306 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%rem>
307 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%lv.2>
382 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
402 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%rem.div>
470 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[P_VAL:%.+]]> = ir<%val>
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| H A D | vplan-sink-scalars-and-merge.ll | 47 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
107 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
186 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
348 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
450 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
565 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
683 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%lv.a>
793 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%div>
853 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED]]> = ir<%lv.a>
876 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%div>
[all …]
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| H A D | interleave-and-scalarize-only.ll | 95 ; DBG-NEXT: PHI-PREDICATED-INSTRUCTION vp<{{.+}}> = ir<%l>
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| H A D | vplan-printing.ll | 224 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%tmp4>
428 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PHI:%.+]]> = ir<%sd1>
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kInstrFormats.td | 470 // M68k INSTRUCTION. Most instructions specify the location of an operand by
503 // M68k PSEUDO INSTRUCTION
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstrFormats.td | 12 // CPU INSTRUCTION FORMATS
666 // FLOATING POINT INSTRUCTION FORMATS
|
| H A D | Mips16InstrFormats.td | 12 // CPU INSTRUCTION FORMATS
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | CloneFunction.cpp | 360 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ in hasRoundingModeOperand() macro
363 #define FUNCTION INSTRUCTION in hasRoundingModeOperand()
|