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Searched refs:HalfVT (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h402 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
403 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
404 return HalfVT; in getHalfSizedIntegerVT()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1691 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
1693 SDValue One = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
1694 SDValue Zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
1708 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1755 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1); in LowerUDIVREM64()
1868 const unsigned halfBitWidth = HalfVT.getSizeInBits(); in LowerUDIVREM64()
1872 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT); in LowerUDIVREM64()
1875 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One); in LowerUDIVREM64()
1883 SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT); in LowerUDIVREM64()
1973 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerSDIVREM() local
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H A DSIISelLowering.cpp5919 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), in lowerBUILD_VECTOR() local
5921 MVT HalfIntVT = MVT::getIntegerVT(HalfVT.getSizeInBits()); in lowerBUILD_VECTOR()
5930 SDValue Lo = DAG.getBuildVector(HalfVT, SL, LoOps); in lowerBUILD_VECTOR()
5931 SDValue Hi = DAG.getBuildVector(HalfVT, SL, HiOps); in lowerBUILD_VECTOR()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp372 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4() local
390 createUnpackShuffleMask(HalfVT, MaskLowTemp, true, false); in interleave8bitStride4()
391 createUnpackShuffleMask(HalfVT, MaskHighTemp, false, false); in interleave8bitStride4()
H A DX86ISelLowering.cpp9371 EVT HalfVT = in EltsFromConsecutiveLoads() local
10491 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getHopForBuildVector() local
17282 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getShuffleHalfVectors() local
17287 return DAG.getUNDEF(HalfVT); in getShuffleHalfVectors()
17300 SDValue Op1 = DAG.getUNDEF(HalfVT); in getShuffleHalfVectors()
17330 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in lowerShuffleWithUndefHalf() local
21836 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in LowerAVXExtend() local
21849 OpHi = DAG.getBitcast(HalfVT, OpHi); in LowerAVXExtend()
25472 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in LowerEXTEND_VECTOR_INREG() local
25482 Hi = DAG.getNode(Opc, dl, HalfVT, Hi); in LowerEXTEND_VECTOR_INREG()
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp1044 EVT HalfVT = in SplitInteger() local
1046 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
H A DLegalizeIntegerTypes.cpp4384 EVT HalfVT = LHSLow.getValueType(); in ExpandIntRes_XMULO() local
4386 SDVTList VTHalfWithO = DAG.getVTList(HalfVT, BitVT); in ExpandIntRes_XMULO()
4388 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT); in ExpandIntRes_XMULO()
4399 SDValue HighSum = DAG.getNode(ISD::ADD, dl, HalfVT, One, Two); in ExpandIntRes_XMULO()
4634 EVT HalfVT = In1.getValueType(); in ExpandIntRes_FunnelShift() local
4643 unsigned HalfVTBits = HalfVT.getScalarSizeInBits(); in ExpandIntRes_FunnelShift()
4657 Lo = DAG.getNode(Opc, DL, HalfVT, Select2, Select1, NewShAmt); in ExpandIntRes_FunnelShift()
4658 Hi = DAG.getNode(Opc, DL, HalfVT, Select3, Select2, NewShAmt); in ExpandIntRes_FunnelShift()
4664 EVT HalfVT = in ExpandIntRes_VSCALE() local
4669 APInt One(HalfVT.getSizeInBits(), 1); in ExpandIntRes_VSCALE()
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H A DDAGCombiner.cpp5619 TLI.isNarrowingProfitable(VT, HalfVT) && in visitANDLike()
5620 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
5621 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
5622 TLI.isTruncateFree(VT, HalfVT) && in visitANDLike()
5623 TLI.isZExtFree(HalfVT, VT)) { in visitANDLike()
9932 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), BW / 2); in visitBSWAP() local
9936 TLI.isTruncateFree(VT, HalfVT) && in visitBSWAP()
9942 Res = DAG.getZExtOrTrunc(Res, DL, HalfVT); in visitBSWAP()
9943 Res = DAG.getNode(ISD::BSWAP, DL, HalfVT, Res); in visitBSWAP()
21907 if (!TLI.isShuffleMaskLegal(Mask0, HalfVT) || in foldShuffleOfConcatUndefs()
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H A DLegalizeVectorTypes.cpp3473 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
3480 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
3482 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
3489 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
3490 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
H A DTargetLowering.cpp2214 EVT HalfVT = Op.getOperand(0).getValueType(); in SimplifyDemandedBits() local
2215 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); in SimplifyDemandedBits()
9449 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in expandVecReduce() local
9450 if (!isOperationLegalOrCustom(BaseOpcode, HalfVT)) in expandVecReduce()
9455 Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi); in expandVecReduce()
9456 VT = HalfVT; in expandVecReduce()
H A DSelectionDAGBuilder.cpp190 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
194 PartVT, HalfVT, V); in getCopyFromParts()
196 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
198 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
199 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11683 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
11685 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
12705 auto *HalfVT = cast<FixedVectorType>(HalfV->getType()); in areExtractShuffleVectors() local
15979 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), in performVectorAddSubExtCombine() local
17197 unsigned NumElts = HalfVT.getVectorNumElements(); in splitStores()
17280 EVT BCVT = MVT::Other, HalfVT = MVT::Other; in performUzpCombine() local
17286 HalfVT = MVT::v8i8; in performUzpCombine()
17290 HalfVT = MVT::v4i16; in performUzpCombine()
17294 HalfVT = MVT::v2i32; in performUzpCombine()
17301 DAG.getUNDEF(HalfVT)); in performUzpCombine()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17704 MVT ExtVT, HalfVT; in PerformMinMaxCombine() local
17706 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
17709 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
17717 DAG.getNode(ARMISD::VQMOVNs, DL, HalfVT, DAG.getUNDEF(HalfVT), in PerformMinMaxCombine()
17744 MVT HalfVT; in PerformMinMaxCombine() local
17747 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
17750 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
17758 DAG.getNode(ARMISD::VQMOVNu, DL, HalfVT, DAG.getUNDEF(HalfVT), N0, in PerformMinMaxCombine()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2739 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in lowerVECTOR_SHUFFLE() local
2740 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVECTOR_SHUFFLE()
2742 V2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V2, in lowerVECTOR_SHUFFLE()