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Searched refs:FirstOp (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegacyLegalizerInfo.h157 const unsigned OpcodeIdx = Aspect.Opcode - FirstOp; in setAction()
182 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeScalarToDifferentSizeStrategy()
193 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeVectorElementToDifferentSizeStrategy()
322 const unsigned OpcodeIdx = Opcode - FirstOp; in setScalarAction()
329 const unsigned OpcodeIdx = Opcode - FirstOp; in setPointerAction()
345 unsigned OpcodeIdx = Opcode - FirstOp; in setScalarInVectorAction()
358 const unsigned OpcodeIdx = Opcode - FirstOp; in setVectorNumElementAction()
465 ScalarSizeChangeStrategies[LastOp - FirstOp + 1];
467 VectorElementSizeChangeStrategies[LastOp - FirstOp + 1];
474 AddrSpace2PointerActions[LastOp - FirstOp + 1];
[all …]
H A DLegalizerInfo.h1272 static const int FirstOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START;
1275 LegalizeRuleSet RulesForOpcode[LastOp - FirstOp + 1];
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp652 unsigned FirstOp = 1; // First CmpMI operand to copy. in convert() local
665 case AArch64::FCMPSrr: Opc = AArch64::FCCMPSrr; FirstOp = 0; break; in convert()
666 case AArch64::FCMPDrr: Opc = AArch64::FCCMPDrr; FirstOp = 0; break; in convert()
667 case AArch64::FCMPESrr: Opc = AArch64::FCCMPESrr; FirstOp = 0; break; in convert()
668 case AArch64::FCMPEDrr: Opc = AArch64::FCCMPEDrr; FirstOp = 0; break; in convert()
672 FirstOp = 0; in convert()
678 FirstOp = 0; in convert()
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
692 if (CmpMI->getOperand(FirstOp + 1).isReg()) in convert()
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
[all …]
H A DAArch64ISelLowering.cpp10951 SDValue FirstOp = N->getOperand(0); in tryLowerToSLI() local
10952 unsigned FirstOpc = FirstOp.getOpcode(); in tryLowerToSLI()
10962 And = FirstOp; in tryLowerToSLI()
10968 Shift = FirstOp; in tryLowerToSLI()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegacyLegalizerInfo.cpp105 for (unsigned OpcodeIdx = 0; OpcodeIdx <= LastOp - FirstOp; ++OpcodeIdx) { in computeTables()
106 const unsigned Opcode = FirstOp + OpcodeIdx; in computeTables()
302 if (Aspect.Opcode < FirstOp || Aspect.Opcode > LastOp) in findScalarLegalAction()
333 if (Aspect.Opcode < FirstOp || Aspect.Opcode > LastOp) in findVectorLegalAction()
364 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
365 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
H A DLegalizerInfo.cpp266 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
267 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
313 assert(OpcodeTo >= FirstOp && OpcodeTo <= LastOp && "Unsupported opcode"); in aliasActionDefinitions()
379 for (unsigned Opcode = FirstOp; Opcode <= LastOp; ++Opcode) { in verify()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineInstr.cpp1622 bool FirstOp = true; in print() local
1654 FirstOp = false; in print()
1660 if (FirstOp) FirstOp = false; else OS << ","; in print()
1728 if (!FirstOp) { in print()
1729 FirstOp = false; in print()
1736 if (!FirstOp) { in print()
1737 FirstOp = false; in print()
1744 if (!FirstOp) { in print()
1745 FirstOp = false; in print()
1753 if (!FirstOp) in print()
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp574 Value *FirstOp = FirstInst->getOperand(I); in foldPHIArgGEPIntoPHI() local
576 PHINode::Create(FirstOp->getType(), E, FirstOp->getName() + ".pn"); in foldPHIArgGEPIntoPHI()
579 NewPN->addIncoming(FirstOp, PN.getIncomingBlock(0)); in foldPHIArgGEPIntoPHI()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DNewGVN.cpp1577 Value *FirstOp = lookupOperandLeader(CmpOp0); in performSymbolicPredicateInfoEvaluation() local
1582 if (shouldSwapOperandsForIntrinsic(FirstOp, SecondOp, I)) { in performSymbolicPredicateInfoEvaluation()
1583 std::swap(FirstOp, SecondOp); in performSymbolicPredicateInfoEvaluation()
1589 return ExprResult::some(createVariableOrConstant(FirstOp), in performSymbolicPredicateInfoEvaluation()
1593 if (Predicate == CmpInst::FCMP_OEQ && isa<ConstantFP>(FirstOp) && in performSymbolicPredicateInfoEvaluation()
1594 !cast<ConstantFP>(FirstOp)->isZero()) in performSymbolicPredicateInfoEvaluation()
1595 return ExprResult::some(createConstantExpression(cast<Constant>(FirstOp)), in performSymbolicPredicateInfoEvaluation()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2348 MachineInstr *FirstOp = nullptr; in RescheduleOps() local
2382 FirstOp = Op; in RescheduleOps()
2404 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp, in RescheduleOps()
2411 MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp; in RescheduleOps()
H A DARMISelLowering.cpp7680 SDValue FirstOp = Op.getOperand(0); in LowerBUILD_VECTOR_i1() local
7681 if (!isa<ConstantSDNode>(FirstOp) && in LowerBUILD_VECTOR_i1()
7683 [&FirstOp](SDUse &U) { in LowerBUILD_VECTOR_i1()
7684 return U.get().isUndef() || U.get() == FirstOp; in LowerBUILD_VECTOR_i1()
7686 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i32, FirstOp, in LowerBUILD_VECTOR_i1()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1496 unsigned FirstOp = CurOp++; in encodeInstruction() local
1503 getX86RegNum(MI.getOperand(FirstOp)), OS); in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp748 MachineOperand FirstOp = MI.getOperand(0); in PredicateInstruction() local
756 .add(FirstOp) in PredicateInstruction()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp7297 unsigned FirstOp; in PeepholePPC64() local
7320 FirstOp = 0; in PeepholePPC64()
7336 FirstOp = 1; in PeepholePPC64()
7344 if (!isa<ConstantSDNode>(N->getOperand(FirstOp))) in PeepholePPC64()
7347 SDValue Base = N->getOperand(FirstOp + 1); in PeepholePPC64()
7408 int Offset = N->getConstantOperandVal(FirstOp); in PeepholePPC64()
7484 if (FirstOp == 1) // Store in PeepholePPC64()
H A DPPCISelLowering.cpp14762 SDValue FirstOp; in isSplatBV() local
14766 FirstOp = Op.getOperand(i); in isSplatBV()
14767 if (!FirstOp.isUndef()) in isSplatBV()
14773 if (Op.getOperand(i) != FirstOp && !Op.getOperand(i).isUndef()) in isSplatBV()
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2050 unsigned FirstOp = 1; in processInstruction() local
2073 FirstOp = 0; in processInstruction()
2088 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO || in processInstruction()
2089 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64) in processInstruction()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DInstructionSimplify.cpp4860 auto FirstOp = static_cast<Instruction::CastOps>(CI->getOpcode()); in simplifyCastInst() local
4868 if (CastInst::isEliminableCastPair(FirstOp, SecondOp, SrcTy, MidTy, DstTy, in simplifyCastInst()