| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 241 FeatureBits.flip(FB); in ToggleFeature()
242 return FeatureBits; in ToggleFeature()
246 FeatureBits ^= FB; in ToggleFeature()
247 return FeatureBits; in ToggleFeature()
253 return FeatureBits; in SetFeatureBitsTransitively()
260 FeatureBits.reset(I); in ClearFeatureBitsTransitively()
264 return FeatureBits; in ClearFeatureBitsTransitively()
278 FeatureBits.set(FeatureEntry->Value); in ToggleFeature()
289 return FeatureBits; in ToggleFeature()
294 return FeatureBits; in ApplyFeatureFlag()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.cpp | 37 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, in computeTargetABI() argument
41 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in computeTargetABI()
66 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
97 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument
98 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate()
100 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) in validate()
102 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) in validate()
107 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
112 if (FeatureBits[Feature.Value] && in parseFeatureBits()
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| H A D | RISCVBaseInfo.h | 361 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
378 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
381 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
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| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 92 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable
112 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits()
114 FeatureBits = FeatureBits_; in setFeatureBits()
120 return FeatureBits[Feature]; in hasFeature()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 182 FeatureBitset FeatureBits = getFeatureBits(); in initializeSubtargetDependencies() local
184 setFeatureBits(FeatureBits.reset(Hexagon::FeatureDuplex)); in initializeSubtargetDependencies()
185 setFeatureBits(Hexagon_MC::completeHVXFeatures(FeatureBits)); in initializeSubtargetDependencies()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 64 const FeatureBitset &FeatureBits = in DecodeGPRRegisterClass() local
66 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in DecodeGPRRegisterClass()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 215 const FeatureBitset &FeatureBits = in DecodeGPRPairRegisterClass() local
217 bool hasHighReg = FeatureBits[CSKY::FeatureHighreg]; in DecodeGPRPairRegisterClass()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2795 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2796 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
4832 const FeatureBitset &FeatureBits = in DecodeThumbTableBranch() local
4977 const FeatureBitset &FeatureBits = in DecodeMSRMask() local
4980 if (FeatureBits[ARM::FeatureMClass]) { in DecodeMSRMask()
5000 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
5008 if (!(FeatureBits[ARM::HasV8MMainlineOps])) in DecodeMSRMask()
5018 if (!(FeatureBits[ARM::Feature8MSecExt])) in DecodeMSRMask()
5037 if (!(FeatureBits[ARM::FeaturePACBTI])) in DecodeMSRMask()
5048 if (!(FeatureBits[ARM::HasV7Ops])) { in DecodeMSRMask()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 866 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
867 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()
873 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()
883 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 215 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local
216 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()
217 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 475 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch() local
476 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch()
477 STI.setFeatureBits(FeatureBits); in selectArch()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5441 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits(); in getMClassRegisterMask() local
5442 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits)) in getMClassRegisterMask()
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