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Searched refs:FalseReg (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp724 Register FalseReg = in convertCmovInstsToBranches() local
728 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
731 FalseReg = FRIt->second; in convertCmovInstsToBranches()
733 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
H A DX86InstrInfo.h362 Register FalseReg) const override;
H A DX86InstrInfo.cpp3340 Register FalseReg, int &CondCycles, in canInsertSelect() argument
3354 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
3378 Register FalseReg) const { in insertSelect()
3386 .addReg(FalseReg) in insertSelect()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp504 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
506 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
530 FalseReg.setImplicit(); in optimizeSelect()
531 NewMI.add(FalseReg); in optimizeSelect()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp922 Register FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
923 if (FalseReg == 0) in selectSelect()
927 std::swap(TrueReg, FalseReg); in selectSelect()
966 .addReg(FalseReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp473 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
478 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
511 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
515 .addReg(FalseReg) in LowerFPToInt()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp540 Register FalseReg, int &CondCycles, in canInsertSelect() argument
552 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
576 Register FalseReg) const { in insertSelect()
596 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
598 FalseReg = FReg; in insertSelect()
609 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h245 Register FalseReg) const override;
H A DSystemZISelLowering.cpp7563 Register FalseReg = MI->getOperand(2).getReg(); in createPHIsForSelects() local
7569 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
7574 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end()) in createPHIsForSelects()
7575 FalseReg = RegRewriteTable[FalseReg].second; in createPHIsForSelects()
7580 .addReg(FalseReg).addMBB(FalseMBB); in createPHIsForSelects()
7583 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1580 Register FalseReg) const { in insertSelect()
1639 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1640 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3137 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3144 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3146 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3148 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3156 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3158 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3160 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h528 Register FalseReg) const override;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp788 auto FalseReg = MIB.getReg(3); in selectSelect() local
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
795 .addUse(FalseReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2364 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2367 const TargetRegisterClass *FalseClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2400 FalseReg.setImplicit(); in optimizeSelect()
2401 NewMI.add(FalseReg); in optimizeSelect()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h310 Register TrueReg, Register FalseReg, int &CondCycles,
316 Register TrueReg, Register FalseReg) const override;
321 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1142 .addReg(FalseReg) in insertVectorSelect()
1157 .addReg(FalseReg) in insertVectorSelect()
1171 .addReg(FalseReg) in insertVectorSelect()
1185 .addReg(FalseReg) in insertVectorSelect()
1201 .addReg(FalseReg) in insertVectorSelect()
1217 .addReg(FalseReg) in insertVectorSelect()
1235 .addReg(FalseReg) in insertVectorSelect()
2771 std::swap(TrueReg, FalseReg); in insertSelect()
2783 .addReg(FalseReg); in insertSelect()
2787 .addReg(FalseReg) in insertSelect()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h889 Register TrueReg, Register FalseReg, in canInsertSelect() argument
913 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h233 Register FalseReg) const override;
H A DAArch64InstrInfo.cpp604 Register FalseReg, int &CondCycles, in canInsertSelect() argument
610 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
632 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
654 Register TrueReg, Register FalseReg) const { in insertSelect()
762 TrueReg = FalseReg; in insertSelect()
764 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
768 FalseReg = NewVReg; in insertSelect()
777 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
782 .addReg(FalseReg) in insertSelect()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp5579 Register FalseReg = Sel.getFalseReg(); in matchSelectToLogical() local
5582 auto *FalseDef = getDefIgnoringCopies(FalseReg, MRI); in matchSelectToLogical()
5596 MIB.buildOr(DstReg, Cond, FalseReg); in matchSelectToLogical()
5604 if (Cond == FalseReg || (MaybeCstFalse && MaybeCstFalse->isZero())) { in matchSelectToLogical()
5622 MIB.buildAnd(DstReg, MIB.buildNot(OpTy, Cond), FalseReg); in matchSelectToLogical()