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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dsitofp_and_uitofp.mir342 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C1]]
352 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C1]]
378 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
390 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
417 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
495 ; FP32: $d0 = COPY [[FSUB]](s64)
504 ; FP64: $d0 = COPY [[FSUB]](s64)
529 ; FP32: $d0 = COPY [[FSUB]](s64)
540 ; FP64: $d0 = COPY [[FSUB]](s64)
566 ; FP32: $d0 = COPY [[FSUB]](s64)
[all …]
H A Dfptosi_and_fptoui.mir341 ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
356 ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
385 ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
402 ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
434 ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
451 ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
523 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
538 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
567 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
584 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
[all …]
H A Dfloat_arithmetic_operations.mir58 ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
59 ; FP32: $f0 = COPY [[FSUB]](s32)
65 ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
66 ; FP64: $f0 = COPY [[FSUB]](s32)
174 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
175 ; FP32: $d0 = COPY [[FSUB]](s64)
181 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
182 ; FP64: $d0 = COPY [[FSUB]](s64)
H A Dfloating_point_vec_arithmetic_operations.mir89 ; P5600: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
90 ; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
117 ; P5600: [[FSUB:%[0-9]+]]:_(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
118 ; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Dfloating_point_vec_arithmetic_operations_builtin.mir101 ; P5600: [[FSUB:%[0-9]+]]:_(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
102 ; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
129 ; P5600: [[FSUB:%[0-9]+]]:_(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
130 ; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-fsub.mir19 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:vgpr(s32) = G_FSUB [[COPY2]], [[COPY3]]
38 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:vgpr(s32) = G_FSUB [[COPY2]], [[COPY1]]
57 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:vgpr(s32) = G_FSUB [[COPY]], [[COPY2]]
75 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:vgpr(s32) = G_FSUB [[COPY]], [[COPY1]]
H A Dlegalize-fsub.mir19 ; SI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
20 ; SI-NEXT: $vgpr0 = COPY [[FSUB]](s32)
26 ; VI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
27 ; VI-NEXT: $vgpr0 = COPY [[FSUB]](s32)
34 ; GFX9-NEXT: $vgpr0 = COPY [[FSUB]](s32)
175 ; SI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[UV2]]
186 ; VI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[UV2]]
265 ; SI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[UV3]]
277 ; VI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[UV3]]
527 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FSUB]](s16)
[all …]
H A Dcombine-redundant-neg.mir15 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
16 ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
35 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY1]], [[COPY]]
36 ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
H A Dlegalize-intrinsic-round.mir20 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
37 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
54 ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
82 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[FSUB]]
229 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
256 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
283 ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
479 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
498 ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
591 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
[all …]
H A Dirtranslator-atomicrmw.ll35 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[PHI1]], [[C]]
36 …%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[PHI1]], [[FSUB]] :: (load store se…
H A Dcombine-foldable-fneg.mir149 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[FNEG]], [[COPY1]]
150 ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
169 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY1]], [[COPY]]
170 ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
599 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
600 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FSUB]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir60 ; FP32: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
61 ; FP32: $f0 = COPY [[FSUB]](s32)
67 ; FP64: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
68 ; FP64: $f0 = COPY [[FSUB]](s32)
180 ; FP32: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
181 ; FP32: $d0 = COPY [[FSUB]](s64)
187 ; FP64: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
188 ; FP64: $d0 = COPY [[FSUB]](s64)
H A Dsitofp_and_uitofp.mir80 ; FP32: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[MV]], [[C1]]
81 ; FP32: $d0 = COPY [[FSUB]](s64)
89 ; FP64: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[MV]], [[C1]]
90 ; FP64: $d0 = COPY [[FSUB]](s64)
H A Dfloating_point_vec_arithmetic_operations.mir92 ; P5600: [[FSUB:%[0-9]+]]:fprb(<4 x s32>) = G_FSUB [[LOAD]], [[LOAD1]]
93 ; P5600: G_STORE [[FSUB]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
121 ; P5600: [[FSUB:%[0-9]+]]:fprb(<2 x s64>) = G_FSUB [[LOAD]], [[LOAD1]]
122 ; P5600: G_STORE [[FSUB]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-fsub-scalar.mir41 ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[TRUNC]], [[TRUNC1]]
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s32)
80 ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[TRUNC]], [[TRUNC1]]
81 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-fp-arith.mir40 ; CHECK: [[FSUB:%[0-9]+]]:_(<2 x s32>) = G_FSUB [[COPY]], [[COPY1]]
41 ; CHECK: $d0 = COPY [[FSUB]](<2 x s32>)
H A Dlegalize-fp-arith-fp16.mir50 ; NO-FP16: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FPEXT]], [[FPEXT1]]
51 ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FSUB]](s32)
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td83 FSUB,
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def113 ADD_BINARY_VVP_OP_COMPACT(FSUB) REGISTER_PACKED(VVP_FSUB)
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def53 DAG_INSTRUCTION(FSub, 2, 1, experimental_constrained_fsub, FSUB)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h391 FSUB, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp327 case ISD::FSUB: in LegalizeOp()
763 case ISD::FSUB: in Expand()
1424 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { in ExpandFNEG()
1428 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero, in ExpandFNEG()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp577 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
593 case ISD::FSUB: in getArithmeticInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp317 { ISD::FSUB, MVT::v2f64, 2 }, // subpd in getArithmeticInstrCost()
671 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
680 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
858 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
859 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
942 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
943 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
944 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
945 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
1036 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Damdgpu-codegenprepare-fold-binop-select.ll489 ; IR-NEXT: [[FSUB:%.*]] = fsub nsz float 1.000000e+00, [[FPEXT]]
490 …NEXT: [[CALL:%.*]] = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[FPEXT]], float [[FSUB]])

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