| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 960 FSINCOS, enumerator
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 201 case ISD::FSINCOS: return "fsincos"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 2244 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3205 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3209 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
4032 case ISD::FSINCOS: in ConvertNodeToLibcall()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 929 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 755 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
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| H A D | X86ISelLowering.cpp | 570 setOperationAction(ISD::FSINCOS, VT, Action); in X86TargetLowering()
624 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
698 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in X86TargetLowering()
704 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in X86TargetLowering()
719 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
788 setOperationAction(ISD::FSINCOS, MVT::f80, Expand); in X86TargetLowering()
844 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall); in X86TargetLowering()
896 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
2286 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in X86TargetLowering()
2287 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in X86TargetLowering()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1728 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1733 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 116 ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in CSKYTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1590 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1639 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | double-intrinsics.ll | 170 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
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| H A D | float-intrinsics.ll | 181 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
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| H A D | double-intrinsics-strict.ll | 172 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
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| H A D | float-intrinsics-strict.ll | 172 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
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| H A D | half-intrinsics.ll | 306 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 423 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in MipsTargetLowering()
424 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in MipsTargetLowering()
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| H A D | MipsSEISelLowering.cpp | 147 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in MipsSETargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 124 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 442 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
591 ISD::FCOS, ISD::FSIN, ISD::FSINCOS, in AArch64TargetLowering()
799 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
800 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
802 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
803 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
1329 setOperationAction(ISD::FSINCOS, VT, Expand); in AArch64TargetLowering()
5508 case ISD::FSINCOS: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1439 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in ARMTargetLowering()
1440 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in ARMTargetLowering()
1482 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in ARMTargetLowering()
1483 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in ARMTargetLowering()
1521 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in ARMTargetLowering()
10437 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 316 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in RISCVTargetLowering()
334 ISD::FSINCOS, ISD::FEXP, ISD::FEXP2, ISD::FLOG, in RISCVTargetLowering()
672 setOperationAction(ISD::FSINCOS, VT, Expand); in RISCVTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 384 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
389 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 470 setOperationAction(ISD::FSINCOS, VT, Expand); in SystemZTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10059 case ISD::FSINCOS: in isCanonicalized()
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