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Searched refs:FSHR (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-fshr.mir21 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY4]], [[COPY5]](s32)
42 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY3]], [[COPY4]](s32)
63 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY1]], [[COPY4]](s32)
84 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY4]], [[COPY2]](s32)
104 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY3]](s32)
124 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY3]], [[COPY2]](s32)
144 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY1]], [[COPY2]](s32)
163 ; CHECK-NEXT: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
H A Dlegalize-rotl-rotr.mir191 ; GFX-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY]], [[SUB]](s32)
192 ; GFX-NEXT: $sgpr0 = COPY [[FSHR]](s32)
314 ; GFX-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV]], [[SUB]](s32)
321 …; GFX-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32), …
403 ; GFX-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY]], [[COPY1]](s32)
404 ; GFX-NEXT: $sgpr0 = COPY [[FSHR]](s32)
464 ; GFX-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV]], [[UV4]](s32)
468 …; GFX-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32), …
H A Dlegalize-fshl.mir19 ; SI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s32)
23 ; SI-NEXT: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[LSHR]], [[FSHR]], [[XOR]](s32)
32 ; VI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s32)
36 ; VI-NEXT: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[LSHR]], [[FSHR]], [[XOR]](s32)
45 ; GFX9-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s32)
49 ; GFX9-NEXT: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[LSHR]], [[FSHR]], [[XOR]](s32)
74 ; SI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[C]](s32)
78 ; SI-NEXT: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[LSHR]], [[FSHR]], [[XOR]](s32)
95 ; VI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[C]](s32)
99 ; VI-NEXT: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[LSHR]], [[FSHR]], [[XOR]](s32)
[all …]
H A Dlegalize-fshr.mir20 ; SI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
21 ; SI-NEXT: $vgpr0 = COPY [[FSHR]](s32)
28 ; VI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
29 ; VI-NEXT: $vgpr0 = COPY [[FSHR]](s32)
36 ; GFX9-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
37 ; GFX9-NEXT: $vgpr0 = COPY [[FSHR]](s32)
60 ; SI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[UV4]](s32)
62 ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32)
73 ; VI-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[UV4]](s32)
75 ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32)
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h697 FSHR, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp338 case ISD::FSHR: in LegalizeOp()
800 case ISD::FSHR: in Expand()
H A DSelectionDAGDumper.cpp256 case ISD::FSHR: return "fshr"; in getOperationName()
H A DLegalizeIntegerTypes.cpp268 case ISD::FSHR: in PromoteIntegerResult()
1303 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift()
1681 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break; in PromoteIntegerOperand()
2554 case ISD::FSHR: in ExpandIntegerResult()
3838 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()
3840 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
4622 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
H A DTargetLowering.cpp1968 case ISD::FSHR: { in SimplifyDemandedBits()
4078 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
4088 if (N0.getOpcode() == ISD::FSHR) in foldSetCCWithFunnelShift()
7154 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
7305 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
9068 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
H A DDAGCombiner.cpp1725 case ISD::FSHR: return visitFunnelShift(N); in visit()
6942 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
7474 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
7475 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
7484 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
7485 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
7505 bool HasFSHR = hasOperation(ISD::FSHR, VT); in MatchRotate()
7672 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
7720 LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
7726 RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
H A DLegalizeVectorTypes.cpp159 case ISD::FSHR: in ScalarizeVectorResult()
1102 case ISD::FSHR: in SplitVectorResult()
3872 case ISD::FSHR: in WidenVectorResult()
H A DLegalizeDAG.cpp1257 case ISD::FSHR: in LegalizeOp()
3406 case ISD::FSHR: in ExpandNode()
H A DSelectionDAG.cpp3301 case ISD::FSHR: in computeKnownBits()
H A DSelectionDAGBuilder.cpp6516 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h40 FSHR, enumerator
H A DX86ISelLowering.cpp215 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1199 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1395 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1834 setOperationAction(ISD::FSHR, MVT::v64i8, Custom); in X86TargetLowering()
1836 setOperationAction(ISD::FSHR, MVT::v32i16, Custom); in X86TargetLowering()
1838 setOperationAction(ISD::FSHR, MVT::v16i32, Custom); in X86TargetLowering()
1910 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
30399 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift()
30547 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
30591 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
[all …]
H A DX86InstrInfo.td143 def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>;
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp801 ISD::FSHL, ISD::FSHR, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1577 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1578 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp293 setOperationAction({ISD::FSHL, ISD::FSHR}, XLenVT, Custom); in RISCVTargetLowering()
297 setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Custom); in RISCVTargetLowering()
3214 case ISD::FSHR: { in LowerOperation()
3232 if (Op.getOpcode() == ISD::FSHR) { in LowerOperation()
7182 case ISD::FSHR: { in ReplaceNodeResults()
7201 if (N->getOpcode() == ISD::FSHR) { in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td398 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp741 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
744 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
11190 case ISD::FSHR: return LowerFunnelShift(Op, DAG); in LowerOperation()
11316 case ISD::FSHR: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp350 setOperationAction(ISD::FSHR, MVT::i32, Legal); in AMDGPUTargetLowering()