| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ |
| H A D | vector-intrinsic-call-cost.ll | 7 ; CHECK-NEXT: [[FSHL:%.+]] = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> undef, <4 x i16> undef, <…
11 ; CHECK-NEXT: store <4 x i16> [[FSHL]], <4 x i16>* [[GEP_BC]], align 2
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 696 FSHL, enumerator
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 337 case ISD::FSHL: in LegalizeOp()
799 case ISD::FSHL: in Expand()
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| H A D | SelectionDAGDumper.cpp | 255 case ISD::FSHL: return "fshl"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 267 case ISD::FSHL: in PromoteIntegerResult()
1680 case ISD::FSHL: in PromoteIntegerOperand()
2553 case ISD::FSHL: in ExpandIntegerResult()
4622 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
4648 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
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| H A D | TargetLowering.cpp | 1967 case ISD::FSHL: in SimplifyDemandedBits()
1972 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
4078 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
7148 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
7154 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
7302 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
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| H A D | DAGCombiner.cpp | 1724 case ISD::FSHL: in visit()
6936 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
7452 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg()
7465 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg()
7466 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); in MatchFunnelPosNeg()
7504 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate()
7672 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
7720 LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
7726 RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
9703 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
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| H A D | LegalizeVectorTypes.cpp | 158 case ISD::FSHL: in ScalarizeVectorResult()
1101 case ISD::FSHL: in SplitVectorResult()
3871 case ISD::FSHL: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 1256 case ISD::FSHL: in LegalizeOp()
3405 case ISD::FSHL: in ExpandNode()
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| H A D | SelectionDAG.cpp | 3300 case ISD::FSHL: in computeKnownBits()
3308 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
3317 if (Opcode == ISD::FSHL) { in computeKnownBits()
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| H A D | SelectionDAGBuilder.cpp | 6516 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 39 FSHL, enumerator
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| H A D | X86TargetTransformInfo.cpp | 3596 { ISD::FSHL, MVT::i64, 4 } in getIntrinsicInstrCost()
3605 { ISD::FSHL, MVT::i32, 4 }, in getIntrinsicInstrCost()
3606 { ISD::FSHL, MVT::i16, 4 }, in getIntrinsicInstrCost()
3607 { ISD::FSHL, MVT::i8, 4 } in getIntrinsicInstrCost()
3618 ISD = ISD::FSHL; in getIntrinsicInstrCost()
3624 ISD = ISD::FSHL; in getIntrinsicInstrCost()
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| H A D | X86ISelLowering.cpp | 215 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1198 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
1394 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
1833 setOperationAction(ISD::FSHL, MVT::v64i8, Custom); in X86TargetLowering()
1835 setOperationAction(ISD::FSHL, MVT::v32i16, Custom); in X86TargetLowering()
1837 setOperationAction(ISD::FSHL, MVT::v16i32, Custom); in X86TargetLowering()
1909 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
30547 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
30591 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
32245 case ISD::FSHL: in LowerOperation()
[all …]
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| H A D | X86InstrInfo.td | 142 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 801 ISD::FSHL, ISD::FSHR, in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1575 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1576 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 293 setOperationAction({ISD::FSHL, ISD::FSHR}, XLenVT, Custom); in RISCVTargetLowering()
297 setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Custom); in RISCVTargetLowering()
3213 case ISD::FSHL: in LowerOperation()
7181 case ISD::FSHL: in ReplaceNodeResults()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 397 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 740 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
743 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
8915 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift()
11189 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation()
11315 case ISD::FSHL: in ReplaceNodeResults()
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