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Searched refs:FROUND (Results 1 – 25 of 26) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def93 DAG_FUNCTION(round, 1, 0, experimental_constrained_round, FROUND)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h928 FROUND, enumerator
H A DBasicTTIImpl.h1745 ISD = ISD::FROUND; in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp505 case Intrinsic::round: Opcode = ISD::FROUND; break; in mightUseCTR()
614 Opcode = ISD::FROUND; break; in mightUseCTR()
H A DPPCISelLowering.cpp446 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
451 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
1008 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
1009 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
1014 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
1015 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
1208 setOperationAction(ISD::FROUND, MVT::f128, Legal); in PPCTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td260 def AMDGPUround : SDNode<"ISD::FROUND",
H A DAMDGPUISelLowering.cpp301 setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
1160 case ISD::FROUND: return LowerFROUND(Op, DAG); in LowerOperation()
H A DAMDGPUISelDAGToDAG.cpp167 case ISD::FROUND: in fp16SrcZerosHighBits()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp212 case ISD::FROUND: return "fround"; in getOperationName()
H A DLegalizeFloatTypes.cpp119 case ISD::FROUND: R = SoftenFloatRes_FROUND(N); break; in SoftenFloatResult()
1259 case ISD::FROUND: ExpandFloatRes_FROUND(N, Lo, Hi); break; in ExpandFloatResult()
2269 case ISD::FROUND: in PromoteFloatResult()
2634 case ISD::FROUND: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp381 case ISD::FROUND: in LegalizeOp()
H A DLegalizeVectorTypes.cpp101 case ISD::FROUND: in ScalarizeVectorResult()
1038 case ISD::FROUND: in SplitVectorResult()
3844 case ISD::FROUND: in WidenVectorResult()
H A DLegalizeDAG.cpp4093 case ISD::FROUND: in ConvertNodeToLibcall()
4838 case ISD::FROUND: in PromoteNode()
H A DSelectionDAGBuilder.cpp6278 case Intrinsic::round: Opcode = ISD::FROUND; break; in visitIntrinsicCall()
8311 if (visitUnaryFloatCall(I, ISD::FROUND)) in visitCall()
H A DSelectionDAG.cpp4628 case ISD::FROUND: in isKnownNeverNaN()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp581 setOperationAction(ISD::FROUND, MVT::f16, Promote); in NVPTXTargetLowering()
582 setOperationAction(ISD::FROUND, MVT::v2f16, Expand); in NVPTXTargetLowering()
583 setOperationAction(ISD::FROUND, MVT::f32, Custom); in NVPTXTargetLowering()
584 setOperationAction(ISD::FROUND, MVT::f64, Custom); in NVPTXTargetLowering()
2241 case ISD::FROUND: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp842 setOperationAction({ISD::FROUND, ISD::FROUNDEVEN, ISD::FPOWI}, VT, Expand); in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp609 ISD::FRINT, ISD::FROUND, ISD::FROUNDEVEN, in AArch64TargetLowering()
638 setOperationAction(ISD::FROUND, MVT::v4f16, Expand); in AArch64TargetLowering()
663 setOperationAction(ISD::FROUND, MVT::v8f16, Expand); in AArch64TargetLowering()
679 ISD::FRINT, ISD::FTRUNC, ISD::FROUND, in AArch64TargetLowering()
958 ISD::FRINT, ISD::FROUND, ISD::FROUNDEVEN, in AArch64TargetLowering()
1105 ISD::FROUND, ISD::FROUNDEVEN, ISD::STRICT_FFLOOR, in AArch64TargetLowering()
1310 setOperationAction(ISD::FROUND, VT, Custom); in AArch64TargetLowering()
1662 setOperationAction(ISD::FROUND, VT, Custom); in addTypeForFixedLengthSVE()
5429 case ISD::FROUND: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp332 ISD::FRINT, ISD::FROUND, ISD::FROUNDEVEN, ISD::FTRUNC, in RISCVTargetLowering()
662 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND}, in RISCVTargetLowering()
904 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND}, in RISCVTargetLowering()
3421 case ISD::FROUND: in LowerOperation()
8490 case ISD::FROUND: return RISCVFPRndMode::RMM; in matchRoundingOp()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp464 setOperationAction(ISD::FROUND, VT, Legal); in SystemZTargetLowering()
524 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in SystemZTargetLowering()
556 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in SystemZTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td500 def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1638 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp154 setOperationAction(ISD::FROUND, MVT::f16, Promote); in MipsSETargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp355 setOperationAction(ISD::FROUND, VT, Legal); in addMVEVectorTypes()
1490 setOperationAction(ISD::FROUND, MVT::f32, Legal); in ARMTargetLowering()
1506 setOperationAction(ISD::FROUND, MVT::f64, Legal); in ARMTargetLowering()
1530 setOperationAction(ISD::FROUND, MVT::f16, Legal); in ARMTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp586 setOperationAction(ISD::FROUND, VT, Action); in X86TargetLowering()
1241 setOperationAction(ISD::FROUND, RoundedTy, Custom); in X86TargetLowering()
1346 setOperationAction(ISD::FROUND, VT, Custom); in X86TargetLowering()
1763 setOperationAction(ISD::FROUND, VT, Custom); in X86TargetLowering()
2080 setOperationAction(ISD::FROUND, MVT::f16, Custom); in X86TargetLowering()
32277 case ISD::FROUND: return LowerFROUND(Op, DAG); in LowerOperation()
43675 case ISD::FROUND: in scalarizeExtEltFP()

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