| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 405 MO.setReg(FPReg); in replaceFPWithRealFP()
822 .addReg(FPReg) in emitPrologue()
1065 .addReg(FPReg) in emitPrologue()
1447 FPReg) in inlineStackProbe()
1452 FPReg) in inlineStackProbe()
1454 .addReg(FPReg); in inlineStackProbe()
1713 RBReg = FPReg; in emitEpilogue()
1721 .addReg(FPReg) in emitEpilogue()
1748 RBReg = FPReg; in emitEpilogue()
1831 if (RBReg == FPReg) in emitEpilogue()
[all …]
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| H A D | PPCFastISel.cpp | 1126 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned); in SelectIToFP() local
1127 if (FPReg == 0) in SelectIToFP()
1142 .addReg(FPReg); in SelectIToFP()
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| /llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContextWindows_x86_64.cpp | 71 } FPReg; typedef
74 (sizeof(GPR) + LLVM_EXTENSION offsetof(FPReg, regname))
78 #reg, NULL, sizeof(((FPReg *)nullptr)->reg), FPR_OFFSET(reg), \
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| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFrameLowering.cpp | 95 Register FPReg = LoongArch::R22; in emitPrologue() local
141 adjustReg(MBB, MBBI, DL, FPReg, SPReg, StackSize, MachineInstr::FrameSetup); in emitPrologue()
145 nullptr, RI->getDwarfRegNum(FPReg, true), 0)); in emitPrologue()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 88 Register FPReg = getFPReg(STI); in emitPrologue() local
151 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), FPReg) in emitPrologue()
157 nullptr, RI->getDwarfRegNum(FPReg, true))); in emitPrologue()
228 Register FPReg = getFPReg(STI); in emitEpilogue() local
263 .addReg(FPReg) in emitEpilogue()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 726 unsigned FPReg; // Frame pointer register member in __anon948350c40111::ARMELFStreamer
1192 FPReg = ARM::SP; in EHReset()
1294 UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); in FlushUnwindOpcodes()
1362 assert((NewSPReg == ARM::SP || NewSPReg == FPReg) && in emitSetFP()
1366 FPReg = NewFPReg; in emitSetFP()
1377 assert(FPReg == ARM::SP && "current FP must be SP"); in emitMovSP()
1381 FPReg = Reg; in emitMovSP()
1385 UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); in emitMovSP()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 610 unsigned FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true); in generateCompactUnwindEncoding() local
613 FPReg = getXRegFromWReg(FPReg); in generateCompactUnwindEncoding()
615 if (LRReg != AArch64::LR || FPReg != AArch64::FP) in generateCompactUnwindEncoding()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 1102 Register FPReg = RegInfo->getFrameRegister(MF); in spillCalleeSavedRegisters() local
1106 bool NeedsFrameRecordPush = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg); in spillCalleeSavedRegisters()
1112 if (NeedsFrameRecordPush && (Reg == FPReg || Reg == ARM::LR)) in spillCalleeSavedRegisters()
1126 !MF.getRegInfo().isLiveIn(Reg) && !(hasFP(MF) && Reg == FPReg)) in spillCalleeSavedRegisters()
1149 Register FPReg = RegInfo->getFrameRegister(MF); in restoreCalleeSavedRegisters() local
1153 bool NeedsFrameRecordPop = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg); in restoreCalleeSavedRegisters()
1159 if (NeedsFrameRecordPop && (Reg == FPReg || Reg == ARM::LR)) in restoreCalleeSavedRegisters()
1174 if ((ARM::tGPRRegClass.contains(Reg)) && !(hasFP(MF) && Reg == FPReg)) in restoreCalleeSavedRegisters()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1676 unsigned FPReg = getFPReg(Op); in handleSpecialFP() local
1682 FPKills |= 1U << FPReg; in handleSpecialFP()
1706 unsigned FPReg = getFPReg(Op); in handleSpecialFP() local
1710 Op.setReg(getSTReg(FPReg)); in handleSpecialFP()
1713 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
1730 unsigned FPReg = countTrailingZeros(FPKills); in handleSpecialFP() local
1731 if (isLive(FPReg)) in handleSpecialFP()
1732 freeStackSlotAfter(Inst, FPReg); in handleSpecialFP()
1733 FPKills &= ~(1U << FPReg); in handleSpecialFP()
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| H A D | X86FrameLowering.cpp | 2623 Register FPReg = TRI->getFrameRegister(MF); in assignCalleeSavedSpillSlots() local
2625 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) { in assignCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 400 Register FPReg = getFPReg(STI); in emitPrologue() local
514 if (STI.isRegisterReservedByUser(FPReg)) in emitPrologue()
518 adjustReg(MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
524 nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize())); in emitPrologue()
599 Register FPReg = getFPReg(STI); in emitEpilogue() local
652 adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset, in emitEpilogue()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kFrameLowering.cpp | 822 Register FPReg = TRI->getFrameRegister(MF); in assignCalleeSavedSpillSlots() local
824 if (TRI->regsOverlap(CSI[i].getReg(), FPReg)) { in assignCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 504 Register FPReg = MFI->getFrameOffsetReg(); in emitEntryFunctionPrologue() local
505 assert(FPReg != AMDGPU::FP_REG); in emitEntryFunctionPrologue()
506 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), FPReg).addImm(0); in emitEntryFunctionPrologue()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 117 int FPReg; member in __anon2aa686d00111::UnwindContext
120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
136 void saveFPReg(int Reg) { FPReg = Reg; } in saveFPReg()
137 int getFPReg() const { return FPReg; } in getFPReg()
176 FPReg = ARM::SP; in reset()
11639 int FPReg = tryParseRegister(); in parseDirectiveSetFP() local
11641 if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") || in parseDirectiveSetFP()
11654 UC.saveFPReg(FPReg); in parseDirectiveSetFP()
11678 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), in parseDirectiveSetFP()
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