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Searched refs:FMINNUM (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-amdgcn.rsq.clamp.mir60 ; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]]
62 ; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]
H A Dcombine-foldable-fneg.mir40 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FNEG]], [[FNEG1]]
41 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
690 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]]
691 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]]
713 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s16) = G_FMINNUM [[TRUNC]], [[C]]
714 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FMINNUM]]
736 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]]
737 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]]
756 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s64) = G_FMINNUM [[COPY]], [[C]]
757 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[FMINNUM]]
H A Dregbankcombiner-clamp-minmax-const.mir449 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY3]]
450 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
569 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMUL]], [[COPY2]]
572 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY3]]
H A Dregbankcombiner-fmed3-minmax-const.mir475 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY2]]
476 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
505 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[COPY]], [[COPY1]]
508 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY2]]
H A Dlegalize-fminnum.mir64 ; SI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
65 ; SI-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
71 ; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
72 ; VI-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
78 ; GFX9-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
79 ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-fp-min-max-intrinsics.ll10 ; CHECK: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
11 ; CHECK: $s0 = COPY [[FMINNUM]](s32)
H A Dlegalize-fminnum.mir22 ; NO-FP16: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FPEXT]], [[FPEXT1]]
23 ; NO-FP16: %minnum:_(s16) = G_FPTRUNC [[FMINNUM]](s32)
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def86 DAG_FUNCTION(minnum, 2, 0, experimental_constrained_minnum, FMINNUM)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h943 FMINNUM, enumerator
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGenericOpcode.rst501 The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
517 definition. This differs from FMINNUM in the handling of signaling NaNs. If one
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp508 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
622 Opcode = ISD::FMINNUM; break; in mightUseCTR()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DGenericOpcodes.td755 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
761 // The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
778 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3424 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { in getTypeBasedIntrinsicInstrCost()
4544 ISD = ISD::FMINNUM; in getMinMaxCost()
4548 {ISD::FMINNUM, MVT::v4f32, 1}, in getMinMaxCost()
4552 {ISD::FMINNUM, MVT::v2f64, 1}, in getMinMaxCost()
4569 {ISD::FMINNUM, MVT::v8f32, 1}, in getMinMaxCost()
4570 {ISD::FMINNUM, MVT::v4f64, 1}, in getMinMaxCost()
4589 {ISD::FMINNUM, MVT::v16f32, 1}, in getMinMaxCost()
4590 {ISD::FMINNUM, MVT::v8f64, 1}, in getMinMaxCost()
4674 ISD = ISD::FMINNUM; in getMinMaxReductionCost()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp360 case ISD::FMINNUM: in LegalizeOp()
813 case ISD::FMINNUM: in Expand()
H A DSelectionDAGDumper.cpp183 case ISD::FMINNUM: return "fminnum"; in getOperationName()
H A DLegalizeFloatTypes.cpp73 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
1217 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
2282 case ISD::FMINNUM: in PromoteFloatResult()
2647 case ISD::FMINNUM: in SoftPromoteHalfResult()
H A DSelectionDAGBuilder.cpp3310 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; in visitSelect()
3312 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) in visitSelect()
3313 Opc = ISD::FMINNUM; in visitSelect()
3317 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? in visitSelect()
3318 ISD::FMINNUM : ISD::FMINIMUM; in visitSelect()
6307 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, in visitIntrinsicCall()
8254 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
H A DTargetLowering.cpp7554 assert((Opcode == ISD::FMINNUM || Opcode == ISD::FMAXNUM || in createSelectForFMINNUM_FMAXNUM()
7559 ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; in createSelectForFMINNUM_FMAXNUM()
7577 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ? in expandFMINNUM_FMAXNUM()
7609 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM; in expandFMINNUM_FMAXNUM()
9577 bool MinMaxLegal = isOperationLegal(ISD::FMINNUM, SrcVT) && in expandFP_TO_INT_SAT()
9585 Clamped = DAG.getNode(ISD::FMINNUM, dl, SrcVT, Clamped, MaxFloatNode); in expandFP_TO_INT_SAT()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp297 ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM, in AMDGPUTargetLowering()
396 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in AMDGPUTargetLowering()
503 case ISD::FMINNUM: in fnegFoldsIntoOp()
3678 return ISD::FMINNUM; in inverseMinMax()
3679 case ISD::FMINNUM: in inverseMinMax()
3796 case ISD::FMINNUM: in performFNegCombine()
H A DSIISelLowering.cpp616 setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, MVT::f16, Custom); in SITargetLowering()
622 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, in SITargetLowering()
726 ISD::FMINNUM, in SITargetLowering()
4715 case ISD::FMINNUM: in LowerOperation()
6848 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
10062 case ISD::FMINNUM: in isCanonicalized()
10303 if (SrcOpc == ISD::FMINNUM || SrcOpc == ISD::FMAXNUM) { in performFCanonicalizeCombine()
10328 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
10501 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
10677 case ISD::FMINNUM: in performExtractVectorEltCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp101 setOperationAction(ISD::FMINNUM, T, Legal); in initializeHVXLowering()
138 setOperationAction(ISD::FMINNUM, P, Custom); in initializeHVXLowering()
2417 case ISD::FMINNUM: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1639 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
1758 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in HexagonTargetLowering()
1807 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp560 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SystemZTargetLowering()
565 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
570 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in SystemZTargetLowering()
575 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
580 setOperationAction(ISD::FMINNUM, MVT::f128, Legal); in SystemZTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp795 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp303 ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT, in RISCVTargetLowering()
660 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, VT, Legal); in RISCVTargetLowering()
899 ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM}, in RISCVTargetLowering()
947 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM}); in RISCVTargetLowering()
3580 case ISD::FMINNUM: in LowerOperation()
7548 case ISD::FMINNUM: in combineBinOpToReduce()
9031 case ISD::FMINNUM: in PerformDAGCombine()

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