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Searched refs:FMAXNUM_IEEE (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fmaxnum.mir25 ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
34 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
43 ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
98 ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
105 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
133 ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
141 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
170 ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
178 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
205 ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
[all …]
H A Dcombine-fcanonicalize.mir112 …; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1…
115 …; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
147 …; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1…
150 …; CHECK-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2…
185 …; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
186 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
218 … ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FMINNUM_IEEE]]
219 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
258 …; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE %zero_undef, [[FCANONICALIZE]]
259 … ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE %one_undef, [[FMAXNUM_IEEE]]
[all …]
H A Dregbankcombiner-fmed3-minmax-const.mir299 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
302 … ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
335 … ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]
336 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
365 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
368 … ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
398 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
401 … ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
436 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
542 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]
[all …]
H A Dlegalize-amdgcn.rsq.clamp.mir30 … ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]]
31 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
H A Dregbankcombiner-clamp-minmax-const.mir375 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
378 … ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
412 … ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]
413 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
531 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY3]]
532 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
H A Dlegalize-fminnum.mir859 … ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
861 ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[FMAXNUM_IEEE]]
872 … ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
874 ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[FMAXNUM_IEEE]]
887 ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[FMAXNUM_IEEE]]
914 ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
917 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
925 ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
928 ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
936 ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
[all …]
H A Dlegalize-vector-args-gfx8-plus.mir372 …; GFX8-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
385 ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FMAXNUM_IEEE]](s16)
433 …; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICA…
440 ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[FMAXNUM_IEEE]](<2 x s16>)
H A Dlegalize-vector-args-gfx7.mir293 ; GFX7-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
294 ; GFX7-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE]](s32)
H A Dcombine-foldable-fneg.mir62 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FNEG]], [[FNEG1]]
63 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h951 FMAXNUM_IEEE, enumerator
H A DTargetLowering.h2628 case ISD::FMAXNUM_IEEE: in isCommutativeBinOp()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp188 case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee"; in getOperationName()
H A DLegalizeVectorOps.cpp363 case ISD::FMAXNUM_IEEE: in LegalizeOp()
H A DLegalizeVectorTypes.cpp124 case ISD::FMAXNUM_IEEE: in ScalarizeVectorResult()
H A DTargetLowering.cpp7578 ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; in expandFMINNUM_FMAXNUM()
H A DDAGCombiner.cpp10075 unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; in combineMinNumMaxNum()
10090 unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE; in combineMinNumMaxNum()
H A DSelectionDAG.cpp4680 case ISD::FMAXNUM_IEEE: { in isKnownNeverNaN()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DGenericOpcodes.td776 // FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
795 // as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
H A DTargetSelectionDAG.td480 def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp441 setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE}, in SITargetLowering()
617 setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE}, MVT::f16, Legal); in SITargetLowering()
619 setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE}, in SITargetLowering()
640 ISD::FMAXNUM_IEEE, ISD::FCANONICALIZE}, in SITargetLowering()
729 ISD::FMAXNUM_IEEE, in SITargetLowering()
4736 case ISD::FMAXNUM_IEEE: in LowerOperation()
10065 case ISD::FMAXNUM_IEEE: in isCanonicalized()
10322 case ISD::FMAXNUM_IEEE: in minMaxOpcToMin3Max3Opc()
10502 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) || in performMinMaxCombine()
10678 case ISD::FMAXNUM_IEEE: in performExtractVectorEltCombine()
[all …]
H A DAMDGPUISelLowering.cpp506 case ISD::FMAXNUM_IEEE: in fnegFoldsIntoOp()
3681 case ISD::FMAXNUM_IEEE: in inverseMinMax()
3684 return ISD::FMAXNUM_IEEE; in inverseMinMax()
3797 case ISD::FMAXNUM_IEEE: in performFNegCombine()
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGenericOpcode.rst538 FMAXNUM_IEEE follow IEEE 754-2008 semantics, FMAXIMUM follows IEEE 754-2018
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp796 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp747 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal); in PPCTargetLowering()
748 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in PPCTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp43664 case ISD::FMAXNUM_IEEE: in scalarizeExtEltFP()