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Searched refs:DstOp (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h65 class DstOp {
74 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
75 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
547 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, in buildUAddo()
553 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, in buildUSubo()
559 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, in buildSAddo()
565 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, in buildSSubo()
584 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, in buildUAdde()
592 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, in buildUSube()
600 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, in buildSAdde()
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H A DCSEMIRBuilder.h56 void profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const;
58 void profileDstOps(ArrayRef<DstOp> Ops, GISelInstProfileBuilder &B) const { in profileDstOps()
59 for (const DstOp &Op : Ops) in profileDstOps()
72 void profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
82 MachineInstrBuilder generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
88 bool checkCopyToDefsPossible(ArrayRef<DstOp> DstOps);
94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
100 MachineInstrBuilder buildConstant(const DstOp &Res,
105 MachineInstrBuilder buildFConstant(const DstOp &Res,
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp399 const DstOp &Dst, const SrcOp &BasePtr, in buildLoadFromOffset()
601 MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge()
612 SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); in buildUnmerge()
620 SmallVector<DstOp, 8> TmpVec(NumReg, Res); in buildUnmerge()
629 SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); in buildUnmerge()
644 MachineIRBuilder::buildBuildVectorConstant(const DstOp &Res, in buildBuildVectorConstant()
661 MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res, in buildBuildVectorTrunc()
744 for (DstOp Result : Results) in buildIntrinsic()
851 unsigned Opcode, const DstOp &OldValRes, in buildAtomicRMW()
1141 [&, this](const DstOp &Op) { in buildInstr()
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H A DCSEMIRBuilder.cpp68 void CSEMIRBuilder::profileDstOp(const DstOp &Op, in profileDstOp()
71 case DstOp::DstType::Ty_RC: in profileDstOp()
74 case DstOp::DstType::Ty_Reg: { in profileDstOp()
136 return llvm::all_of(DstOps, [](const DstOp &Op) { in checkCopyToDefsPossible()
137 DstOp::DstType DT = Op.getDstOpKind(); in checkCopyToDefsPossible()
138 return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC; in checkCopyToDefsPossible()
143 CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps, in generateCopiesIfRequired()
148 const DstOp &Op = DstOps[0]; in generateCopiesIfRequired()
149 if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg) in generateCopiesIfRequired()
241 const DstOp &Dst = DstOps[0]; in buildInstr()
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H A DLegalizerHelper.cpp3639 static void makeDstOps(SmallVectorImpl<DstOp> &DstOps, LLT Ty, in makeDstOps()
3702 SmallVector<SmallVector<DstOp, 8>, 2> OutputOpsPieces(NumDefs); in fewerElementsVectorMultiEltType()
3732 SmallVector<DstOp, 2> Defs; in fewerElementsVectorMultiEltType()
3766 SmallVector<DstOp, 8> OutputOpsPieces; in fewerElementsVectorPhi()
7130 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, in SwapN()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp121 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), in INITIALIZE_PASS_DEPENDENCY()
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), in INITIALIZE_PASS_DEPENDENCY()
138 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp189 auto DstOp = I->getOperand(0); in copyPhysReg() local
191 assert(DstOp.isReg() && SrcOp.isReg() && in copyPhysReg()
194 MRI.replaceRegWith(DstOp.getReg(), SrcOp.getReg()); in copyPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstrRelaxTables.cpp130 Table.push_back({Entry.DstOp, Entry.KeyOp}); in X86ShortFormTable()
155 return I->DstOp; in getShortOpcodeArith()
162 return I->DstOp; in getRelaxedOpcodeArith()
H A DX86InstrRelaxTables.h25 uint16_t DstOp; member
/llvm-project-15.0.7/llvm/lib/Linker/
H A DIRMover.cpp1300 MDNode *DstOp; in linkModuleFlagsMetadata() local
1302 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1317 if (!DstOp) { in linkModuleFlagsMetadata()
1329 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1341 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1379 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1390 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1396 << *DstOp->getOperand(2) << "' from " << DstM.getModuleIdentifier() in linkModuleFlagsMetadata()
1404 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1423 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp88 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
90 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
91 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp57 auto *DstOp = in EmitMOPS() local
69 DAG.setNodeMemRefs(Node, {DstOp}); in EmitMOPS()
75 DAG.setNodeMemRefs(Node, {DstOp, SrcOp}); in EmitMOPS()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFoldTables.h70 uint16_t DstOp; member
H A DX86MCInstLower.cpp1849 const MachineOperand &DstOp = MI->getOperand(0); in getShuffleComment() local
1853 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; in getShuffleComment()
2213 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2214 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
2292 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2293 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
2401 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2402 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
H A DX86InstrInfo.cpp6112 unsigned Opcode = I->DstOp; in foldMemoryOperandImpl()
6850 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
6998 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
7135 return I->DstOp; in getOpcodeAfterMemoryUnfold()
H A DX86InstrFoldTables.cpp6157 Table.push_back({Entry.DstOp, Entry.KeyOp, in addTableEntry()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMIRYamlMapping.h494 unsigned DstOp;
498 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
499 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
508 YamlIO.mapRequired("dstop", Sub.DstOp);
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp95 LLT MemTy, const DstOp &Res, Register Addr) { in assignValueToAddress()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1509 const MachineOperand &DstOp = MI->getOperand(0); in verifyPreISelGenericInstruction() local
1513 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) { in verifyPreISelGenericInstruction()
1781 const MachineOperand &DstOp = MI->getOperand(0); in visitMachineInstrBefore() local
1784 const Register DstReg = DstOp.getReg(); in visitMachineInstrBefore()
1826 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) { in visitMachineInstrBefore()
H A DMachineScheduler.cpp1829 const MachineOperand &DstOp = Copy->getOperand(0); in constrainLocalCopy() local
1830 Register DstReg = DstOp.getReg(); in constrainLocalCopy()
1831 if (!Register::isVirtualRegister(DstReg) || DstOp.isDead()) in constrainLocalCopy()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp274 MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, LLT MemTy, in buildLoad()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp4746 Record *DstOp = Dst->getOperator(); in createInstructionRenderer() local
4747 if (!DstOp->isSubClassOf("Instruction")) { in createInstructionRenderer()
4748 if (DstOp->isSubClassOf("ValueType")) in createInstructionRenderer()
4753 CodeGenInstruction *DstI = &Target.getInstruction(DstOp); in createInstructionRenderer()
5242 Record *DstOp = Dst->getOperator(); in runOnPattern() local
5243 if (!DstOp->isSubClassOf("Instruction")) in runOnPattern()
5246 auto &DstI = Target.getInstruction(DstOp); in runOnPattern()
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp442 {Sub.DstInst, Sub.DstOp}, Sub.Subreg); in setupDebugValueTracking()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp224 std::initializer_list<llvm::DstOp> DstOps,
4434 unsigned Opcode, std::initializer_list<llvm::DstOp> DstOps, in emitInstr()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td6478 bit WithStride, DAGOperand DstOp>
6480 [!con((ins DstOp:$dst),