| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | BDCE.cpp | 115 APInt Demanded = DB.getDemandedBits(SE); in bitTrackingDCE() local
119 if (Demanded.countLeadingZeros() >= (DestBitSize - SrcBitSize)) { in bitTrackingDCE()
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | add-sub-nsw-nuw.ll | 5 ; Demanded bits analysis must disable nsw/nuw when it makes a
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| H A D | combine-avx2-intrinsics.ll | 86 ; Demanded Elts
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| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/X86/ |
| H A D | x86-f16c-inseltpoison.ll | 8 ; Vector Demanded Elts
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| H A D | x86-f16c.ll | 8 ; Vector Demanded Elts
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| H A D | x86-addsub.ll | 11 ; Demanded Elts
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| H A D | x86-addsub-inseltpoison.ll | 11 ; Demanded Elts
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| H A D | x86-sse4a-inseltpoison.ll | 289 ; Vector Demanded Bits
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| H A D | x86-sse4a.ll | 289 ; Vector Demanded Bits
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| H A D | x86-pack.ll | 205 ; Demanded Elts
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| H A D | x86-pack-inseltpoison.ll | 205 ; Demanded Elts
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| H A D | x86-pshufb-inseltpoison.ll | 471 ; Demanded elts tests.
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| H A D | x86-pshufb.ll | 471 ; Demanded elts tests.
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 31 const APInt &Demanded) { in ShrinkDemandedConstant() argument
42 if (C->isSubsetOf(Demanded)) in ShrinkDemandedConstant()
46 I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded)); in ShrinkDemandedConstant()
1253 APInt Demanded, APInt &Undef) { in SimplifyDemandedVectorElts() argument
1256 if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) { in SimplifyDemandedVectorElts()
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| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | icmp-mul-and.ll | 18 ; TODO: Demanded bits does not convert the mul to shift,
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| H A D | shuffle_select-inseltpoison.ll | 1324 ; Demanded elements + simplification can remove the mul alone, but that's not the best case.
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| H A D | shuffle_select.ll | 1339 ; Demanded elements + simplification can remove the mul alone, but that's not the best case.
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| H A D | and.ll | 509 ; Demanded bit analysis allows us to eliminate the add.
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| H A D | vec_shuffle-inseltpoison.ll | 1455 ; Demanded vector elements may not be able to simplify a shuffle mask
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| H A D | vec_shuffle.ll | 1456 ; Demanded vector elements may not be able to simplify a shuffle mask
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2787 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24); in simplifyMul24() local
2792 SDValue DemandedLHS = TLI.SimplifyMultipleUseDemandedBits(LHS, Demanded, DAG); in simplifyMul24()
2793 SDValue DemandedRHS = TLI.SimplifyMultipleUseDemandedBits(RHS, Demanded, DAG); in simplifyMul24()
2801 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI)) in simplifyMul24()
2803 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI)) in simplifyMul24()
4116 APInt Demanded = APInt::getBitsSet(32, in PerformDAGCombine() local
4124 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) || in PerformDAGCombine()
4125 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) { in PerformDAGCombine()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3595 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 554 const APInt &Demanded, in ShrinkDemandedOp() argument
576 unsigned DemandedSize = Demanded.getActiveBits(); in ShrinkDemandedOp()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1735 const APInt &Demanded, in optimizeLogicalImm() argument
1748 uint64_t DemandedBits = Demanded.getZExtValue(); in optimizeLogicalImm()
1803 assert(((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 && in optimizeLogicalImm()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 19921 unsigned Demanded = DemandedBits.getZExtValue(); in targetShrinkDemandedConstant() local
19922 unsigned ShrunkMask = Mask & Demanded; in targetShrinkDemandedConstant()
19923 unsigned ExpandedMask = Mask | ~Demanded; in targetShrinkDemandedConstant()
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