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Searched refs:DefI (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp233 DefI->eraseFromParent(); in processPredicateGPR()
255 assert(DefI); in getPredRegFor()
256 unsigned Opc = DefI->getOpcode(); in getPredRegFor()
258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
259 RegisterSubReg PR = DefI->getOperand(1); in getPredRegFor()
265 MachineBasicBlock &B = *DefI->getParent(); in getPredRegFor()
266 DebugLoc DL = DefI->getDebugLoc(); in getPredRegFor()
272 if (isConvertibleToPredForm(DefI)) { in getPredRegFor()
273 MachineBasicBlock::iterator DefIt = DefI; in getPredRegFor()
329 if (!DefI) in isScalarPred()
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H A DHexagonExpandCondsets.cpp344 if (HII->isPredicated(*DefI)) in updateKillFlags()
421 Defs.insert(DefI->getParent()); in updateDeadsInRange()
422 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
475 for (auto &Op : DefI->operands()) { in updateDeadsInRange()
492 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
499 MachineOperand &Op = DefI->getOperand(i); in updateDeadsInRange()
523 DefI->tieOperands(P.second, DefI->getNumOperands()-1); in updateDeadsInRange()
961 if (!DefI || !isPredicable(DefI)) in predicate()
1045 if (DefI->mayLoadOrStore()) in predicate()
1046 if (!canMoveMemTo(*DefI, TfrI, true)) in predicate()
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H A DHexagonVExtract.cpp149 MachineInstr *DefI = MRI.getVRegDef(VecR); in runOnMachineFunction() local
150 MachineBasicBlock::iterator At = std::next(DefI->getIterator()); in runOnMachineFunction()
151 MachineBasicBlock &DefB = *DefI->getParent(); in runOnMachineFunction()
155 Register AddrR = EmitAddr(DefB, At, DefI->getDebugLoc(), FI, 0); in runOnMachineFunction()
156 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc)) in runOnMachineFunction()
H A DHexagonSplitDouble.cpp235 MachineInstr *DefI = MRI->getVRegDef(R); in partitionRegisters() local
239 if (!DefI || isFixedInstr(DefI)) in partitionRegisters()
404 const MachineInstr *DefI = MRI->getVRegDef(Reg); in profit() local
405 switch (DefI->getOpcode()) { in profit()
413 return profit(DefI); in profit()
426 MachineInstr *DefI = MRI->getVRegDef(DR); in isProfitable() local
427 int32_t P = profit(DefI); in isProfitable()
1135 MachineInstr *DefI = MRI->getVRegDef(DR); in splitPartition() local
1136 SplitIns.insert(DefI); in splitPartition()
H A DHexagonGenInsert.cpp1007 const MachineInstr *DefI = MRI->getVRegDef(R); in findRemovableRegisters() local
1008 assert(DefI); in findRemovableRegisters()
1012 if (DefI->isPHI()) in findRemovableRegisters()
1014 getInstrUses(DefI, Regs[OtherS]); in findRemovableRegisters()
1143 const MachineInstr *DefI = MRI->getVRegDef(IR); in pruneUsesTooFar() local
1146 unsigned DIV = distance(DefI, DefV, RPO, M); in pruneUsesTooFar()
1329 const MachineInstr *DefI = MRI->getVRegDef(I->first); in selectCandidates() local
1330 getInstrUses(DefI, Us); in selectCandidates()
1427 MachineInstr *DefI = MRI->getVRegDef(I.first); in generateInserts() local
1429 DefI->eraseFromParent(); in generateInserts()
H A DHexagonEarlyIfConv.cpp408 const MachineInstr *DefI = MRI->getVRegDef(R); in usesUndefVReg() local
410 assert(DefI && "Expecting a reaching def in MRI"); in usesUndefVReg()
411 if (DefI->isImplicitDef()) in usesUndefVReg()
H A DHexagonConstExtenders.cpp1506 const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr; in calculatePlacement() local
1510 assert(!DefI || MDT->dominates(DefI->getParent(), DomB)); in calculatePlacement()
H A DHexagonBitSimplify.cpp2323 MachineInstr *DefI = MRI.getVRegDef(Op0.getReg()); in genBitSplit() local
2324 assert(DefI != nullptr); in genBitSplit()
2325 if (!MDT.dominates(DefI, &*At)) in genBitSplit()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp316 const MachineInstr *DefI = Def->getParent(); in isSafeToMove() local
318 assert(DefI->getParent() == Insert->getParent()); in isSafeToMove()
332 if (Def != DefI->defs().begin()) in isSafeToMove()
349 const MachineBasicBlock *MBB = DefI->getParent(); in isSafeToMove()
358 if (WebAssembly::isCatch(DefI->getOpcode())) in isSafeToMove()
363 for (const MachineOperand &MO : DefI->operands()) { in isSafeToMove()
393 query(*DefI, Read, Write, Effects, StackPointer); in isSafeToMove()
850 if (!DefI) in runOnMachineFunction()
855 if (DefI->isInlineAsm()) in runOnMachineFunction()
872 bool SameBlock = DefI->getParent() == &MBB; in runOnMachineFunction()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMIRCanonicalizerPass.cpp229 MachineBasicBlock::iterator DefI = BBE; in rescheduleCanonically() local
234 if (DefI != BBE && UseI != BBE) in rescheduleCanonically()
238 DefI = BBI; in rescheduleCanonically()
248 if (DefI == BBE || UseI == BBE) in rescheduleCanonically()
253 DefI->dump(); in rescheduleCanonically()
260 MBB->splice(UseI, MBB, DefI); in rescheduleCanonically()
H A DMachineTraceMetrics.cpp639 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg); in DataDep() local
640 assert(!DefI.atEnd() && "Register has no defs"); in DataDep()
641 DefMI = DefI->getParent(); in DataDep()
642 DefOp = DefI.getOperandNo(); in DataDep()
643 assert((++DefI).atEnd() && "Register has multiple defs"); in DataDep()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp804 MachineInstr *DefI = Def->getInstr(); in adjustSchedDependency() local
807 if (DefI->isBundle()) { in adjustSchedDependency()
810 MachineBasicBlock::const_instr_iterator I(DefI->getIterator()); in adjustSchedDependency()
811 MachineBasicBlock::const_instr_iterator E(DefI->getParent()->instr_end()); in adjustSchedDependency()
825 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI); in adjustSchedDependency()
838 DefI, DefOpIdx, UseI, UseOpIdx)); in adjustSchedDependency()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DDeadStoreElimination.cpp1692 Instruction *DefI = Def->getMemoryInst(); in eliminateDeadWritesAtEndOfFunction() local
1693 auto DefLoc = getLocForWrite(DefI); in eliminateDeadWritesAtEndOfFunction()
1694 if (!DefLoc || !isRemovable(DefI)) in eliminateDeadWritesAtEndOfFunction()
1710 deleteDeadInstruction(DefI); in eliminateDeadWritesAtEndOfFunction()
1722 Instruction *DefI = Def->getMemoryInst(); in tryFoldIntoCalloc() local
1723 MemSetInst *MemSet = dyn_cast<MemSetInst>(DefI); in tryFoldIntoCalloc()
1731 if (!isRemovable(DefI)) in tryFoldIntoCalloc()
1800 Instruction *DefI = Def->getMemoryInst(); in storeIsNoop() local
1801 StoreInst *Store = dyn_cast<StoreInst>(DefI); in storeIsNoop()
1802 MemSetInst *MemSet = dyn_cast<MemSetInst>(DefI); in storeIsNoop()
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/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DLoopInfo.h1213 auto *DefI = dyn_cast<Instruction>(U.get()); in movementPreservesLCSSAForm() local
1214 if (!DefI) in movementPreservesLCSSAForm()
1220 auto *DefBlock = DefI->getParent(); in movementPreservesLCSSAForm()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1161 auto *DefI = dyn_cast<Instruction>(Def); in getInsertPointForUses() local
1162 if (!DefI) in getInsertPointForUses()
1165 assert(DT->dominates(DefI, InsertPt) && "def does not dominate all uses"); in getInsertPointForUses()
1167 auto *L = LI->getLoopFor(DefI->getParent()); in getInsertPointForUses()
/llvm-project-15.0.7/clang/utils/TableGen/
H A DNeonEmitter.cpp1404 DefInit *DefI = cast<DefInit>(DI->getOperator()); in emitDag() local
1405 std::string Op = DefI->getAsString(); in emitDag()
/llvm-project-15.0.7/llvm/lib/TableGen/
H A DRecord.cpp2280 if (DefInit *DefI = dyn_cast<DefInit>(Val)) in getOperatorAsDef() local
2281 return DefI->getDef(); in getOperatorAsDef()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolution.cpp2857 auto *DefI = getDefiningScopeBound(LIOps); in getAddExpr() local
2859 if (!isGuaranteedToTransferExecutionTo(DefI, ReachI)) in getAddExpr()
7022 if (auto *DefI = getNonTrivialDefiningScopeBound(S)) { in getDefiningScopeBound() local
7023 if (!Bound || DT.dominates(Bound, DefI)) in getDefiningScopeBound()
7024 Bound = DefI; in getDefiningScopeBound()
7083 auto *DefI = getDefiningScopeBound(SCEVOps); in isSCEVExprNeverPoison() local
7084 return isGuaranteedToTransferExecutionTo(DefI, I); in isSCEVExprNeverPoison()