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Searched refs:CondReg (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp773 if (!CondReg && !InvCondReg) in getCondOrInverseInReg()
776 if (CondReg) in getCondOrInverseInReg()
777 return {CondReg, false}; in getCondOrInverseInReg()
828 if (!CondReg) in rewriteArithmetic()
838 .addReg(CondReg) in rewriteArithmetic()
854 unsigned CondReg; in rewriteCMov() local
856 std::tie(CondReg, Inverted) = in rewriteCMov()
880 unsigned CondReg; in rewriteFCMov() local
922 unsigned CondReg; in rewriteCondJmp() local
959 if (!CondReg) in rewriteSetCC()
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H A DX86FastISel.cpp2115 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2116 if (CondReg == 0) in X86FastEmitCMoveSelect()
2121 unsigned KCondReg = CondReg; in X86FastEmitCMoveSelect()
2124 TII.get(TargetOpcode::COPY), CondReg) in X86FastEmitCMoveSelect()
2126 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitCMoveSelect()
2129 .addReg(CondReg) in X86FastEmitCMoveSelect()
2315 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
2316 if (CondReg == 0) in X86FastEmitPseudoSelect()
2321 unsigned KCondReg = CondReg; in X86FastEmitPseudoSelect()
2326 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitPseudoSelect()
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H A DX86InstructionSelector.cpp1365 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
1370 .addReg(CondReg) in selectCondBranch()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp90 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
105 if (A->modifiesRegister(CondReg, TRI)) { in optimizeVccBranch()
106 if (!A->definesRegister(CondReg, TRI) || in optimizeVccBranch()
111 ReadsCond |= A->readsRegister(CondReg, TRI); in optimizeVccBranch()
148 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && in optimizeVccBranch()
175 if (!MI.killsRegister(CondReg, TRI)) { in optimizeVccBranch()
178 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
181 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
238 MI.removeOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI)); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp39 MCRegister CondReg; member in __anon6b0c42990111::SIOptimizeExecMaskingPreRA
132 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
269 (CmpReg == Register(CondReg) && in optimizeVcndVcmpPair()
272 return MI.readsRegister(CondReg, TRI); in optimizeVcndVcmpPair()
388 CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC); in runOnMachineFunction()
H A DAMDGPURegisterBankInfo.cpp843 Register CondReg; in executeInWaterfallLoop() local
906 if (!CondReg) { in executeInWaterfallLoop()
907 CondReg = CmpReg; in executeInWaterfallLoop()
909 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
910 MRI.setRegBank(CondReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
925 .addReg(CondReg) in executeInWaterfallLoop()
927 MRI.setRegClass(CondReg, WaveRC); in executeInWaterfallLoop()
932 .addReg(CondReg, RegState::Kill); in executeInWaterfallLoop()
934 MRI.setSimpleHint(NewExec, CondReg); in executeInWaterfallLoop()
2269 Register CondReg = MI.getOperand(0).getReg(); in applyMappingImpl() local
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H A DSIInstrInfo.cpp2644 CondReg.setIsUndef(OrigCond.isUndef()); in preserveCondRegFlags()
2645 CondReg.setIsKill(OrigCond.isKill()); in preserveCondRegFlags()
2699 CondReg.setIsUndef(Cond[1].isUndef()); in insertBranch()
2700 CondReg.setIsKill(Cond[1].isKill()); in insertBranch()
5493 Register CondReg = AMDGPU::NoRegister; in emitLoadSRsrcFromVGPRLoop() local
5537 CondReg = NewCondReg; in emitLoadSRsrcFromVGPRLoop()
5541 .addReg(CondReg) in emitLoadSRsrcFromVGPRLoop()
5543 CondReg = AndReg; in emitLoadSRsrcFromVGPRLoop()
5563 MRI.setSimpleHint(SaveExec, CondReg); in emitLoadSRsrcFromVGPRLoop()
5567 .addReg(CondReg, RegState::Kill); in emitLoadSRsrcFromVGPRLoop()
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H A DAMDGPUInstructionSelector.cpp2480 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
2492 if (!isVCC(CondReg, *MRI)) { in selectG_BRCOND()
2493 if (MRI->getType(CondReg) != LLT::scalar(32)) in selectG_BRCOND()
2504 if (!isVCmpResult(CondReg, *MRI)) { in selectG_BRCOND()
2511 .addReg(CondReg) in selectG_BRCOND()
2513 CondReg = TmpReg; in selectG_BRCOND()
2521 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
2522 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
2525 .addReg(CondReg); in selectG_BRCOND()
H A DVOP3Instructions.td744 class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
748 (i1 CondReg)),
H A DAMDGPUMachineCFGStructurizer.cpp1848 Register CondReg = Cond[0].getReg(); in ensureCondIsNotKilled() local
1849 for (MachineOperand &MO : MRI->use_operands(CondReg)) in ensureCondIsNotKilled()
H A DAMDGPUISelDAGToDAG.cpp2264 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
2291 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); in SelectBRCOND()
H A DSIISelLowering.cpp3601 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
3620 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg) in emitLoadM0FromVGPRLoop()
3628 .addReg(CondReg, RegState::Kill); in emitLoadM0FromVGPRLoop()
3630 MRI.setSimpleHint(NewExec, CondReg); in emitLoadM0FromVGPRLoop()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp913 unsigned CondReg = in selectSelect() local
915 if (CondReg == 0) in selectSelect()
967 .addReg(CondReg); in selectSelect()
1314 unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not); in selectBr() local
1315 if (CondReg == 0) in selectBr()
1324 .addReg(CondReg); in selectBr()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp961 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
962 if (CondReg == 0) in selectBranch()
965 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true); in selectBranch()
1040 Register CondReg = getRegForValue(Cond); in selectSelect() local
1042 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1049 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true)) in selectSelect()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp774 auto CondReg = MIB.getReg(1); in selectSelect() local
775 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
778 .addUse(CondReg) in selectSelect()
H A DARMFastISel.cpp1610 Register CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
1611 if (CondReg == 0) return false; in SelectSelect()
1637 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1640 .addReg(CondReg) in SelectSelect()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2457 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2458 if (!CondReg) in selectBranch()
2471 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2472 if (CondReg == 0) in selectBranch()
2484 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2693 Register CondReg = getRegForValue(Cond); in selectSelect() local
2694 if (!CondReg) in selectSelect()
2742 Register CondReg = getRegForValue(Cond); in selectSelect() local
2743 if (!CondReg) in selectSelect()
2747 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp786 Register CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
789 CondReg, PPCPred)) in SelectBranch()
794 .addReg(CondReg) in SelectBranch()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1711 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
1712 MachineInstr *CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1725 emitTestBit(CondReg, /*Bit = */ 0, /*IsNegative = */ true, in selectCompareBranch()
1733 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
3344 const Register CondReg = Sel.getCondReg(); in select() local
3354 auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg}) in select()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp4865 Register CondReg = MI.getOperand(1).getReg(); in moreElementsVector() local
4867 LLT CondTy = MRI.getType(CondReg); in moreElementsVector()
4875 auto ShufSplat = MIRBuilder.buildShuffleSplat(MoreTy, CondReg); in moreElementsVector()
5402 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
5403 LLT CondTy = MRI.getType(CondReg); in narrowScalarSelect()
5425 CondReg, Src1Regs[I], Src2Regs[I]); in narrowScalarSelect()
5431 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); in narrowScalarSelect()