Lines Matching refs:CondReg
2642 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags() argument
2644 CondReg.setIsUndef(OrigCond.isUndef()); in preserveCondRegFlags()
2645 CondReg.setIsKill(OrigCond.isKill()); in preserveCondRegFlags()
2698 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
2699 CondReg.setIsUndef(Cond[1].isUndef()); in insertBranch()
2700 CondReg.setIsKill(Cond[1].isKill()); in insertBranch()
5493 Register CondReg = AMDGPU::NoRegister; in emitLoadSRsrcFromVGPRLoop() local
5536 if (CondReg == AMDGPU::NoRegister) // First. in emitLoadSRsrcFromVGPRLoop()
5537 CondReg = NewCondReg; in emitLoadSRsrcFromVGPRLoop()
5541 .addReg(CondReg) in emitLoadSRsrcFromVGPRLoop()
5543 CondReg = AndReg; in emitLoadSRsrcFromVGPRLoop()
5563 MRI.setSimpleHint(SaveExec, CondReg); in emitLoadSRsrcFromVGPRLoop()
5567 .addReg(CondReg, RegState::Kill); in emitLoadSRsrcFromVGPRLoop()
6183 Register CondReg = Inst.getOperand(1).getReg(); in moveToVALU() local
6184 bool IsSCC = CondReg == AMDGPU::SCC; in moveToVALU()
6190 .addReg(IsSCC ? VCC : CondReg); in moveToVALU()
6320 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); in moveToVALU() local
6322 BuildMI(*MBB, Inst, Inst.getDebugLoc(), NewDesc, CondReg) in moveToVALU()
6328 addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg); in moveToVALU()