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Searched refs:BUILTIN_OP_END (Results 1 – 25 of 43) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1307 BUILTIN_OP_END enumerator
1313 static const int FIRST_TARGET_STRICTFP_OPCODE = BUILTIN_OP_END + 400;
1319 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END + 500;
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.h31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
H A DARCISelLowering.cpp113 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) in ARCTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
H A DBPFISelDAGToDAG.cpp266 if (OP1N->getOpcode() <= ISD::BUILTIN_OP_END || OP1N->getNumOperands() == 0) in PreprocessLoad()
277 } else if (LDAddrNode->getOpcode() > ISD::BUILTIN_OP_END && in PreprocessLoad()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h24 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.h26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.h27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.h33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h347 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.h59 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h35 OP_BEGIN = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h57 FIRST_NUMBER = ISD::BUILTIN_OP_END,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp61 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
H A DTargetLowering.cpp892 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) in SimplifyMultipleUseDemandedBits()
2685 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { in SimplifyDemandedBits()
3417 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { in SimplifyDemandedVectorElts()
3448 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || in computeKnownBitsForTargetNode()
3482 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || in ComputeNumSignBitsForTargetNode()
3500 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || in SimplifyDemandedVectorEltsForTargetNode()
3512 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || in SimplifyDemandedBitsForTargetNode()
3526 (Op.getOpcode() >= ISD::BUILTIN_OP_END || in SimplifyMultipleUseDemandedBitsForTargetNode()
3560 (Op.getOpcode() >= ISD::BUILTIN_OP_END || in isGuaranteedNotToBeUndefOrPoisonForTargetNode()
3573 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || in isKnownNeverNaNForTargetNode()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h48 FIRST_NUMBER = ISD::BUILTIN_OP_END,

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