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Searched refs:AssertZext (Results 1 – 25 of 40) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr55846.ll4 ; After legalization, this could be: "i8 truncate (i64 AssertZext X, Type: i9)"
5 ; The AssertZext does not add information, so it should be eliminated,
H A DTruncAssertZext.ll4 ; the source of the zext is an AssertZext node
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dassertzext-trunc.ll17 ; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
35 ; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32))
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dzext-lid.ll44 ; which is a special case as an AssertZext from width 0 is invalid.
H A Dcaptured-frame-index.ll181 ; on the leftover AssertZext's ValueType operand.
H A Dfunction-returns.ll473 ; AssertZext inserted. Not using it introduces the spills.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h62 AssertZext, enumerator
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td760 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
761 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
788 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
789 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
790 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
791 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
792 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
793 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
794 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
795 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
H A DHexagonISelDAGToDAG.cpp1533 case ISD::AssertZext: in keepsLowBits()
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dstore-replicated-vals.ll203 ; A replication of a non-local value (ISD::AssertZext case).
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp107 case ISD::AssertZext: return "AssertZext"; in getOperationName()
H A DLegalizeIntegerTypes.cpp60 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
298 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
705 ? ISD::AssertZext in PromoteIntRes_FP_TO_XINT()
2412 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
3225 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
3229 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
H A DLegalizeVectorOps.cpp678 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT()
H A DSelectionDAGBuilder.cpp891 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
5479 case ISD::AssertZext: in getUnderlyingArgRegs()
9236 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, in lowerRangeToAssertZExt()
9993 AssertOp = ISD::AssertZext; in LowerCallTo()
10546 AssertOp = ISD::AssertZext; in LowerArguments()
10586 if (Res.getOpcode() == ISD::AssertZext) in LowerArguments()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp344 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp150 if (Op1->getOpcode() == ISD::AssertZext || in lowerUINT_TO_FP()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1697 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
2490 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
2527 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
2546 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
2727 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
6130 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
6773 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Val, in lowerWorkitemID()
9609 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()
11730 if (Op.getOpcode() == ISD::AssertZext) in isFrameIndexOp()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp471 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
819 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp470 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp262 if (TruncInput.getOpcode() == ISD::AssertZext && in MatchingStackOffset()
916 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp484 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL}); in MipsTargetLowering()
3546 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3608 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp662 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1428 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1269 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrCompiler.td1419 // be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
1428 N->getOpcode() != ISD::AssertZext &&

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