| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 36 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
40 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
61 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
65 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
86 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
91 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
[all …]
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| H A D | PPCFastISel.cpp | 185 SmallVectorImpl<unsigned> &ArgRegs,
1375 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument
1432 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1603 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local
1608 ArgRegs.reserve(NumArgs); in fastLowerCall()
1637 ArgRegs.push_back(Arg); in fastLowerCall()
1646 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 409 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in lowerFormalArguments() local
410 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in lowerFormalArguments()
414 if (ArgRegs.size() == Idx) in lowerFormalArguments()
419 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
426 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
427 MIRBuilder.getMBB().addLiveIn(ArgRegs[I]); in lowerFormalArguments()
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
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| H A D | MipsISelLowering.cpp | 4416 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
4427 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4476 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4499 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local
4500 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs()
4511 if (ArgRegs.size() == Idx) in writeVarArgRegs()
4516 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
4528 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs()
4530 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 559 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local
562 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments()
563 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCallArguments()
570 MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4, in LowerCallArguments()
574 for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) { in LowerCallArguments()
577 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCallArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.h | 56 SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
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| H A D | AMDGPUCallLowering.cpp | 741 … SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs, in passSpecialInputs() argument
830 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
928 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 217 SmallVectorImpl<Register> &ArgRegs,
1876 SmallVectorImpl<Register> &ArgRegs, in ProcessCallArgs() argument
1943 Register Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2224 SmallVector<Register, 8> ArgRegs; in ARMEmitLibcall() local
2228 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2243 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2251 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2333 SmallVector<Register, 8> ArgRegs; in SelectCall() local
2338 ArgRegs.reserve(arg_size); in SelectCall()
2376 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 362 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(GPRArgRegs); in LowerFormalArguments() local
363 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
376 if (ArgRegs.size() == Idx) { in LowerFormalArguments()
380 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
391 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments()
394 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 578 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1343 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
1347 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
1348 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1352 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1362 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 83 ArrayRef<ArrayRef<Register>> ArgRegs, in lowerCall() argument
120 ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(CB, i), in lowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 143 static const MCPhysReg ArgRegs[] = { in CC_SkipOdd() local
147 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_SkipOdd()
148 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_SkipOdd()
152 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 581 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
584 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32()
585 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3231 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local
3275 ArgRegs.push_back(ResultReg); in fastLowerCall()
3307 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11011 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); in LowerFormalArguments() local
11012 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
11025 if (ArgRegs.size() == Idx) { in LowerFormalArguments()
11029 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
11048 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments()
11051 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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