| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerI1Copies.cpp | 57 unsigned AndOp; member in __anone83803c50111::SILowerI1Copies
461 AndOp = AMDGPU::S_AND_B32; in runOnMachineFunction()
469 AndOp = AMDGPU::S_AND_B64; in runOnMachineFunction()
868 BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg) in buildMergeLaneMasks()
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| /llvm-project-15.0.7/mlir/lib/Dialect/LLVMIR/Transforms/ |
| H A D | OptimizeForNVVM.cpp | 71 Value exp = rewriter.create<LLVM::AndOp>(loc, i32Type, cast, mask); in matchAndRewrite()
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| /llvm-project-15.0.7/llvm/lib/TableGen/ |
| H A D | SetTheory.cpp | 62 struct AndOp : public SetTheory::Operator { struct
259 addOperator("and", std::make_unique<AndOp>()); in SetTheory()
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| /llvm-project-15.0.7/mlir/lib/Conversion/ArithmeticToLLVM/ |
| H A D | ArithmeticToLLVM.cpp | 36 using AndIOpLowering = VectorConvertToLLVMPattern<arith::AndIOp, LLVM::AndOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kFrameLowering.cpp | 202 unsigned AndOp = M68k::AND32di; in BuildStackAlignAND() local
214 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Tmp) in BuildStackAlignAND()
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| /llvm-project-15.0.7/mlir/lib/Conversion/SPIRVToLLVM/ |
| H A D | SPIRVToLLVM.cpp | 374 rewriter.create<LLVM::AndOp>(loc, dstType, op.base(), mask); in matchAndRewrite()
511 rewriter.replaceOpWithNewOp<LLVM::AndOp>(op, dstType, shiftedBase, mask); in matchAndRewrite()
1466 DirectConversionPattern<spirv::BitwiseAndOp, LLVM::AndOp>, in populateSPIRVToLLVMConversionPatterns()
1533 DirectConversionPattern<spirv::LogicalAndOp, LLVM::AndOp>, in populateSPIRVToLLVMConversionPatterns()
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| /llvm-project-15.0.7/mlir/lib/Conversion/SCFToOpenMP/ |
| H A D | SCFToOpenMP.cpp | 275 if (matchSimpleReduction<arith::AndIOp, LLVM::AndOp>(reduction)) { in declareReduction()
|
| /llvm-project-15.0.7/mlir/lib/Conversion/AsyncToLLVM/ |
| H A D | AsyncToLLVM.cpp | 362 rewriter.create<LLVM::AndOp>(op->getLoc(), coroSize, negCoroAlign); in matchAndRewrite()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 1219 unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val); in BuildStackAlignAND() local
1260 BuildMI(entryMBB, DL, TII.get(AndOp), FinalStackProbed) in BuildStackAlignAND()
1357 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg) in BuildStackAlignAND()
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| /llvm-project-15.0.7/mlir/lib/Conversion/VectorToLLVM/ |
| H A D | ConvertVectorToLLVM.cpp | 475 LLVM::AndOp>( in matchAndRewrite()
|
| /llvm-project-15.0.7/mlir/lib/Target/LLVMIR/Dialect/OpenMP/ |
| H A D | OpenMPToLLVMIRTranslation.cpp | 1048 .Case([&](LLVM::AndOp) { return llvm::AtomicRMWInst::BinOp::And; }) in convertBinOpToAtomic() argument
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 1089 auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask); in emitBitTestCase() local
1091 Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), AndOp, CstZero) in emitBitTestCase()
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| /llvm-project-15.0.7/flang/lib/Optimizer/CodeGen/ |
| H A D | CodeGen.cpp | 255 rewriter.create<mlir::LLVM::AndOp>(loc, attrTy, attribute, attrMask); in genBoxAttributeCheck()
718 rewriter.replaceOpWithNewOp<mlir::LLVM::AndOp>(cmp, resTy, cp); in matchAndRewrite()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6806 SDValue AndOp; in LowerVSETCC() local
6808 AndOp = Op0; in LowerVSETCC()
6810 AndOp = Op1; in LowerVSETCC()
6813 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) in LowerVSETCC()
6814 AndOp = AndOp.getOperand(0); in LowerVSETCC()
6816 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { in LowerVSETCC()
6817 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0)); in LowerVSETCC()
6818 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1)); in LowerVSETCC()
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| /llvm-project-15.0.7/mlir/lib/Conversion/MemRefToLLVM/ |
| H A D | MemRefToLLVM.cpp | 302 rewriter.create<LLVM::AndOp>(loc, ptrValue, mask), zero)); in matchAndRewrite()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 2859 SDValue AndOp = DAG.getNode(ISD::AND, dl, in visitBitTestCase() local
2863 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE); in visitBitTestCase()
|