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Searched refs:AddrReg (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp223 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local
234 .addReg(AddrReg); in doAtomicBinOpExpansion()
248 .addReg(AddrReg) in doAtomicBinOpExpansion()
300 .addReg(AddrReg); in doMaskedAtomicBinOpExpansion()
333 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
440 .addReg(AddrReg); in expandAtomicMinMaxOp()
492 .addReg(AddrReg) in expandAtomicMinMaxOp()
548 .addReg(AddrReg); in expandAtomicCmpXchg()
557 .addReg(AddrReg) in expandAtomicCmpXchg()
570 .addReg(AddrReg); in expandAtomicCmpXchg()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
114 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
117 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore() local
68 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg) in expandStore()
74 .addReg(AddrReg) in expandStore()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp63 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
65 return AddrReg.getReg(0); in getStackAddress()
158 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); in getStackAddress() local
160 return AddrReg.getReg(0); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp116 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); in getStackAddress() local
118 return AddrReg.getReg(0); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp1099 unsigned AddrReg; in buildIndirectWrite() local
1102 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1103 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1104 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1105 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1112 AddrReg, ValueReg) in buildIndirectWrite()
1131 unsigned AddrReg; in buildIndirectRead() local
1134 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1135 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1136 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
[all …]
H A DSILoadStoreOptimizer.cpp119 const MachineOperand *AddrReg[MaxAddressRegs]; member
127 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) { in hasSameBaseAddress()
147 const MachineOperand *AddrOp = AddrReg[i]; in hasMergeableAddress()
721 AddrReg[J] = &I->getOperand(AddrIdx[J]); in setMI()
1120 Register BaseReg = AddrReg->getReg(); in mergeRead2Pair()
1121 unsigned BaseSubReg = AddrReg->getSubReg(); in mergeRead2Pair()
1133 .addReg(AddrReg->getReg(), 0, BaseSubReg) in mergeRead2Pair()
1188 const MachineOperand *AddrReg = in mergeWrite2Pair() local
1212 Register BaseReg = AddrReg->getReg(); in mergeWrite2Pair()
1213 unsigned BaseSubReg = AddrReg->getSubReg(); in mergeWrite2Pair()
[all …]
H A DAMDGPUCallLowering.cpp100 auto AddrReg = MIRBuilder.buildFrameIndex( in getStackAddress() local
103 return AddrReg.getReg(0); in getStackAddress()
213 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress() local
215 return AddrReg.getReg(0); in getStackAddress()
H A DAMDGPULegalizerInfo.cpp4766 Register AddrReg = SrcOp.getReg(); in packImage16bitOpsToDwords() local
4772 (B.getMRI()->getType(AddrReg) == S16)) { in packImage16bitOpsToDwords()
4777 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
4783 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0); in packImage16bitOpsToDwords()
4784 PackedAddrs.push_back(AddrReg); in packImage16bitOpsToDwords()
4798 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
4803 V2S16, {AddrReg, MI.getOperand(ArgOffset + I + 1).getReg()}) in packImage16bitOpsToDwords()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp507 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
521 AddrReg = MI.getOperand(1).getReg(); in optimizeLdStInterleave()
575 .addReg(AddrReg) in optimizeLdStInterleave()
615 .addReg(AddrReg) in optimizeLdStInterleave()
620 .addReg(AddrReg) in optimizeLdStInterleave()
H A DAArch64ExpandPseudoInsts.cpp196 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
218 .addReg(AddrReg); in expandCMP_SWAP()
235 .addReg(AddrReg); in expandCMP_SWAP()
276 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
324 .addReg(AddrReg); in expandCMP_SWAP_128()
353 .addReg(AddrReg); in expandCMP_SWAP_128()
367 .addReg(AddrReg); in expandCMP_SWAP_128()
H A DAArch64FastISel.cpp230 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
2037 unsigned AddrReg, in emitStoreRelease() argument
2050 AddrReg = constrainOperandRegClass(II, AddrReg, 1); in emitStoreRelease()
2053 .addReg(AddrReg) in emitStoreRelease()
2177 Register AddrReg = getRegForValue(PtrV); in selectStore() local
2178 return emitStoreRelease(VT, SrcReg, AddrReg, in selectStore()
2496 Register AddrReg = getRegForValue(BI->getOperand(0)); in selectIndirectBr() local
2497 if (AddrReg == 0) in selectIndirectBr()
2502 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs()); in selectIndirectBr()
4993 const Register AddrReg = constrainOperandRegClass( in selectAtomicCmpXchg() local
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
104 return AddrReg.getReg(0); in getStackAddress()
H A DX86SpeculativeLoadHardening.cpp1161 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1163 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg) in tracePredStateThroughIndirectBranches()
1174 .addReg(AddrReg, RegState::Kill); in tracePredStateThroughIndirectBranches()
H A DX86InstructionSelector.cpp1411 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); in materializeFP() local
1412 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg) in materializeFP()
1421 AddrReg) in materializeFP()
H A DX86FastISel.cpp3770 Register AddrReg = createResultReg(&X86::GR64RegClass); in X86MaterializeFP() local
3772 AddrReg) in X86MaterializeFP()
3776 addRegReg(MIB, AddrReg, false, PICBase, false); in X86MaterializeFP()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp147 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); in getStackAddress() local
148 return AddrReg.getReg(0); in getStackAddress()
268 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
271 return AddrReg.getReg(0); in getStackAddress()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
109 return AddrReg.getReg(0); in getStackAddress()
H A DARMExpandPseudoInsts.cpp1731 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP() local
1769 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1793 .addReg(AddrReg); in ExpandCMP_SWAP()
1861 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP_64() local
1889 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1918 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
H A DARMFastISel.cpp1321 Register AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1322 if (AddrReg == 0) return false; in SelectIndirectBr()
1328 TII.get(Opc)).addReg(AddrReg)); in SelectIndirectBr()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp239 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
240 return AddrReg.getReg(0); in getStackAddress()
H A DMipsISelLowering.cpp2560 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; in lowerEH_RETURN() local
2562 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); in lowerEH_RETURN()
2565 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), in lowerEH_RETURN()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1861 Register AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1862 if (AddrReg == 0) in SelectIndirectBr()
1866 .addReg(AddrReg); in SelectIndirectBr()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp749 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); in printInst() local
750 O << ", [" << getRegisterName(AddrReg) << ']'; in printInst()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp4030 Register AddrReg = LdStMI.getPointerReg(); in reduceLoadStoreWidth() local
4056 LLT PtrTy = MRI.getType(AddrReg); in reduceLoadStoreWidth()
4076 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); in reduceLoadStoreWidth()