119     const MachineOperand *AddrReg[MaxAddressRegs];  member
127         if (AddrReg[i]->isImm() || AddrRegNext.isImm()) {  in hasSameBaseAddress()
128           if (AddrReg[i]->isImm() != AddrRegNext.isImm() ||  in hasSameBaseAddress()
129               AddrReg[i]->getImm() != AddrRegNext.getImm()) {  in hasSameBaseAddress()
137         if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||  in hasSameBaseAddress()
138             AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {  in hasSameBaseAddress()
147         const MachineOperand *AddrOp = AddrReg[i];  in hasMergeableAddress()
721     AddrReg[J] = &I->getOperand(AddrIdx[J]);  in setMI()
1091   const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);  in mergeRead2Pair()  local
1120   Register BaseReg = AddrReg->getReg();  in mergeRead2Pair()
1121   unsigned BaseSubReg = AddrReg->getSubReg();  in mergeRead2Pair()
1133         .addReg(AddrReg->getReg(), 0, BaseSubReg)  in mergeRead2Pair()
1188   const MachineOperand *AddrReg =  in mergeWrite2Pair()  local
1212   Register BaseReg = AddrReg->getReg();  in mergeWrite2Pair()
1213   unsigned BaseSubReg = AddrReg->getSubReg();  in mergeWrite2Pair()
1225         .addReg(AddrReg->getReg(), 0, BaseSubReg)  in mergeWrite2Pair()