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Searched refs:AVGCEILU (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h649 AVGCEILU, enumerator
H A DTargetLowering.h2634 case ISD::AVGCEILU: in isCommutativeBinOp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h375 X86_INTRINSIC_DATA(avx2_pavg_b, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
376 X86_INTRINSIC_DATA(avx2_pavg_w, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
822 X86_INTRINSIC_DATA(avx512_pavg_b_512, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
823 X86_INTRINSIC_DATA(avx512_pavg_w_512, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
1285 X86_INTRINSIC_DATA(sse2_pavg_b, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
1286 X86_INTRINSIC_DATA(sse2_pavg_w, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
H A DX86ISelLowering.cpp1039 setOperationAction(ISD::AVGCEILU, MVT::v16i8, Legal); in X86TargetLowering()
1040 setOperationAction(ISD::AVGCEILU, MVT::v8i16, Legal); in X86TargetLowering()
1460 setOperationAction(ISD::AVGCEILU, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1461 setOperationAction(ISD::AVGCEILU, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1787 setOperationAction(ISD::AVGCEILU, MVT::v32i16, HasBWI ? Legal : Custom); in X86TargetLowering()
1788 setOperationAction(ISD::AVGCEILU, MVT::v64i8, HasBWI ? Legal : Custom); in X86TargetLowering()
32347 case ISD::AVGCEILU: return LowerAVG(Op, Subtarget, DAG); in LowerOperation()
48874 return DAG.getNode(ISD::AVGCEILU, DL, Ops[0].getValueType(), Ops); in detectAVGPattern()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp235 case ISD::AVGCEILU: return "avgceilu"; in getOperationName()
H A DSelectionDAG.cpp3218 case ISD::AVGCEILU: { in computeKnownBits()
5501 case ISD::AVGCEILU: { in FoldValue()
H A DLegalizeVectorTypes.cpp3726 case ISD::AVGCEILU: in WidenVectorResult()
H A DTargetLowering.cpp1030 unsigned AVGOpc = IsCeil ? (IsSigned ? ISD::AVGCEILS : ISD::AVGCEILU) in combineShiftToAVG()
H A DDAGCombiner.cpp1707 case ISD::AVGCEILU: return visitAVG(N); in visit()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp829 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td381 def avgceilu : SDNode<"ISD::AVGCEILU" , SDTIntBinOp, [SDNPCommutative]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1049 setOperationAction(ISD::AVGCEILU, VT, Legal); in AArch64TargetLowering()
4806 : (IsRoundingAdd ? ISD::AVGCEILU : ISD::AVGFLOORU); in LowerINTRINSIC_WO_CHAIN()
15272 (N0Opc == ISD::AVGCEILU || N0Opc == ISD::AVGCEILS || in performConcatVectorsCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp279 setOperationAction(ISD::AVGCEILU, VT, Legal); in addMVEVectorTypes()
15414 case ISD::AVGCEILU: in FlattenVectorShuffle()