Searched refs:AVGCEILS (Results 1 – 11 of 11) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 648 AVGCEILS, enumerator
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| H A D | TargetLowering.h | 2633 case ISD::AVGCEILS: in isCommutativeBinOp()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 236 case ISD::AVGCEILS: return "avgceils"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 3725 case ISD::AVGCEILS: in WidenVectorResult()
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| H A D | TargetLowering.cpp | 1030 unsigned AVGOpc = IsCeil ? (IsSigned ? ISD::AVGCEILS : ISD::AVGCEILU) in combineShiftToAVG()
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| H A D | SelectionDAG.cpp | 5495 case ISD::AVGCEILS: { in FoldValue()
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| H A D | DAGCombiner.cpp | 1706 case ISD::AVGCEILS: in visit()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 829 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 380 def avgceils : SDNode<"ISD::AVGCEILS" , SDTIntBinOp, [SDNPCommutative]>;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1048 setOperationAction(ISD::AVGCEILS, VT, Legal); in AArch64TargetLowering()
4805 ? (IsRoundingAdd ? ISD::AVGCEILS : ISD::AVGFLOORS) in LowerINTRINSIC_WO_CHAIN()
15272 (N0Opc == ISD::AVGCEILU || N0Opc == ISD::AVGCEILS || in performConcatVectorsCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 278 setOperationAction(ISD::AVGCEILS, VT, Legal); in addMVEVectorTypes()
15413 case ISD::AVGCEILS: in FlattenVectorShuffle()
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