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Searched refs:ATOMIC_CMP_SWAP (Results 1 – 25 of 27) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2010-10-08-cmpxchg8b.ll7 ; X86TargetLowering::ReplaceNodeResults, case ATOMIC_CMP_SWAP.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1170 ATOMIC_CMP_SWAP, enumerator
H A DSelectionDAGNodes.h1391 case ISD::ATOMIC_CMP_SWAP:
1445 return Op == ISD::ATOMIC_CMP_SWAP ||
1458 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h503 ATOMIC_CMP_SWAP, enumerator
H A DAMDGPUInstrInfo.td255 def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
H A DAMDGPUInstructions.td408 def atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
H A DSIISelLowering.cpp371 setOperationAction(ISD::ATOMIC_CMP_SWAP, {MVT::i32, MVT::i64}, Custom); in SITargetLowering()
754 ISD::ATOMIC_CMP_SWAP, in SITargetLowering()
4663 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG); in LowerOperation()
9314 return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(), in LowerATOMIC_CMP_SWAP()
12633 case AMDGPUISD::ATOMIC_CMP_SWAP: in isSDNodeSourceOfDivergence()
H A DAMDGPUISelLowering.cpp4379 NODE_NAME_CASE(ATOMIC_CMP_SWAP) in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h341 ATOMIC_CMP_SWAP, enumerator
H A DSystemZOperators.td390 def z_atomic_cmp_swap : SDNode<"SystemZISD::ATOMIC_CMP_SWAP",
H A DSystemZISelLowering.cpp4306 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAP, in lowerATOMIC_CMP_SWAP()
6022 OPCODE(ATOMIC_CMP_SWAP); in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp131 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); in Mips16TargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp83 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
H A DLegalizeDAG.cpp2778 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs, in ExpandNode()
2801 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs, in ExpandNode()
3955 case ISD::ATOMIC_CMP_SWAP: { in ConvertNodeToLibcall()
H A DLegalizeIntegerTypes.cpp229 case ISD::ATOMIC_CMP_SWAP: in PromoteIntegerResult()
2459 case ISD::ATOMIC_CMP_SWAP: { in ExpandIntegerResult()
2469 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs, in ExpandIntegerResult()
H A DSelectionDAG.cpp803 case ISD::ATOMIC_CMP_SWAP: in AddNodeIDCustom()
3785 case ISD::ATOMIC_CMP_SWAP: in computeKnownBits()
4409 case ISD::ATOMIC_CMP_SWAP: in ComputeNumSignBits()
7539 assert(Opcode == ISD::ATOMIC_CMP_SWAP || in getAtomicCmpSwap()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp547 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
598 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DAtomics-64.ll4 ; code for ATOMIC_CMP_SWAP. Currently, it is inserting 32-bit instructions with
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp137 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); in AVRTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2700 case ISD::ATOMIC_CMP_SWAP: in isI32Insn()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp712 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); in AArch64TargetLowering()
721 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, LibCall); in AArch64TargetLowering()
722 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, LibCall); in AArch64TargetLowering()
723 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, LibCall); in AArch64TargetLowering()
724 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, LibCall); in AArch64TargetLowering()
725 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, LibCall); in AArch64TargetLowering()
20287 case ISD::ATOMIC_CMP_SWAP: in ReplaceNodeResults()
H A DAArch64ISelDAGToDAG.cpp3532 case ISD::ATOMIC_CMP_SWAP: in Select()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td624 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1704 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp5375 case ISD::ATOMIC_CMP_SWAP: in Select()

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