| /llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/ |
| H A D | fastmath2_ldlib_asm.S | 89 lmanta = ASR(lmanta, expa)
90 lmantb = ASR(lmantb, expb)
188 lmanta = ASR(lmanta, expa)
189 lmantb = ASR(lmantb, expb)
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| H A D | fastmath2_dlib_asm.S | 96 lmanta = ASR(lmanta, expa)
97 lmantb = ASR(lmantb, expb)
197 lmanta = ASR(lmanta, expa)
198 lmantb = ASR(lmantb, expb)
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| H A D | fastmath_dlib_asm.S | 104 lmanta = ASR(lmanta, expa)
105 lmantb = ASR(lmantb, expb)
239 lmanta = ASR(lmanta, expa)
240 lmantb = ASR(lmantb, expb)
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| H A D | dfdiv.S | 169 DIV_ITER1B(ASR,1,15,)
170 DIV_ITER1B(ASR,16,15,)
171 DIV_ITER1B(ASR,31,15,PROD=# ( 0 );)
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| H A D | dfaddsub.S | 117 BTMP = ASR(BTMP,EXPDIFF)
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kInstrShiftRotate.td | 15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
95 defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 37 ASR, enumerator
58 case AArch64_AM::ASR: return "asr"; in getShiftExtendName()
79 case 2: return AArch64_AM::ASR; in getShiftType()
107 case AArch64_AM::ASR: STEnc = 2; break; in getShifterImm()
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| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | idioms.ll | 4 ; simplified into a single ASR operation:
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | thumb1.txt | 65 # ASR (immediate)
76 # ASR (register)
|
| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 46 ASR, ///< Arithmetic shift right. enumerator
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| H A D | AVRISelLowering.cpp | 251 NODE(ASR); in getTargetNodeName()
316 Opc8 = AVRISD::ASR; in LowerShifts()
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| /llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 155 static inline uint32_t ASR(const uint32_t value, const uint32_t amount, in ASR() function
|
| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 102 @ ASR (immediate)
120 @ ASR (register)
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| H A D | thumb-diagnostics.s | 45 @ Out of range immediates for ASR instruction.
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| H A D | thumb2-narrow-dp.ll | 417 // ASR
423 ASR r0, r1, r0 // Must use wide encoding as not flag-setting
|
| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ |
| H A D | if-pred-non-void.ll | 15 ; CHECK-NEXT: [[ASR6:%.*]] = bitcast i32* [[ASR:%.*]] to i8*
21 ; CHECK-NEXT: [[SCEVGEP7:%.*]] = getelementptr i32, i32* [[ASR]], i64 128
54 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[ASR]], i64 [[TMP0]]
155 ; CHECK-NEXT: [[ISR:%.*]] = getelementptr inbounds i32, i32* [[ASR]], i64 [[INDVARS_IV]]
190 ; UNROLL-NO-VF-NEXT: [[ASR6:%.*]] = bitcast i32* [[ASR:%.*]] to i8*
198 ; UNROLL-NO-VF-NEXT: [[SCEVGEP7:%.*]] = getelementptr i32, i32* [[ASR]], i64 128
236 ; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[ASR]], i64 [[INDUCTION]]
237 ; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ASR]], i64 [[INDUCTION31]]
315 ; UNROLL-NO-VF-NEXT: [[ISR:%.*]] = getelementptr inbounds i32, i32* [[ASR]], i64 [[INDVARS_IV]]
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| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | FunctionComparator.cpp | 701 unsigned int ASR = GEPR->getPointerAddressSpace(); in cmpGEPs() local
703 if (int Res = cmpNumbers(ASL, ASR)) in cmpGEPs()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 50 def CheckShiftASR : CheckImmOperand_s<3, "AArch64_AM::ASR">;
|
| H A D | AArch64SchedNeoverseN2.td | 1601 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]$",
1602 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]$",
1603 "^(ASR|LSL|LSR)_ZPmI_[BHSD]$",
1604 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]$",
1605 "^(ASR|LSL|LSR)_ZZI_[BHSD]$",
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 554 ASR, enumerator
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 363 (add Y, (sequence "ASR%u", 1, 31))>;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1337 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1432 ST == AArch64_AM::ASR) && getShiftExtendAmount() < width; in isArithmeticShifter()
1443 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
3200 .Case("asr", AArch64_AM::ASR) in tryParseOptionalShiftExtend()
3223 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | sve-intrinsics-shifts.ll | 5 ; ASR
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| H A D | sve-intrinsics-shifts-merging.ll | 5 ; ASR
|