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Searched refs:ANY_EXTEND_VECTOR_INREG (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h792 ANY_EXTEND_VECTOR_INREG, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp388 case ISD::ANY_EXTEND_VECTOR_INREG: in LegalizeOp()
719 case ISD::ANY_EXTEND_VECTOR_INREG: in Expand()
1040 SDValue Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src); in ExpandSIGN_EXTEND_VECTOR_INREG()
H A DLegalizeVectorTypes.cpp70 case ISD::ANY_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
429 case ISD::ANY_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
1002 case ISD::ANY_EXTEND_VECTOR_INREG: in SplitVectorResult()
2751 case ISD::ANY_EXTEND_VECTOR_INREG: in SplitVectorOperand()
3800 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVectorResult()
4308 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
4436 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4450 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
5582 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
H A DSelectionDAGDumper.cpp343 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg"; in getOperationName()
H A DTargetLowering.cpp825 case ISD::ANY_EXTEND_VECTOR_INREG: in SimplifyMultipleUseDemandedBits()
2252 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
2289 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
2325 case ISD::ANY_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
2330 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
3251 case ISD::ANY_EXTEND_VECTOR_INREG: in SimplifyDemandedVectorElts()
3264 if (IsLE && Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG && in SimplifyDemandedVectorElts()
H A DLegalizeIntegerTypes.cpp131 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
5455 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
H A DSelectionDAG.cpp2672 case ISD::ANY_EXTEND_VECTOR_INREG: in isSplatValue()
3489 case ISD::ANY_EXTEND_VECTOR_INREG: { in computeKnownBits()
5306 case ISD::ANY_EXTEND_VECTOR_INREG: in getNode()
H A DDAGCombiner.cpp13015 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
22126 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT)) in combineShuffleToVectorExtend()
22128 DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, in combineShuffleToVectorExtend()
22152 if (Opcode != ISD::ANY_EXTEND_VECTOR_INREG && in combineTruncationShuffle()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp206 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom); in initializeHVXLowering()
251 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom); in initializeHVXLowering()
1901 assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG); in LowerHvxExtend()
2462 case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG); in LowerHvxOperation()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp847 ISD::ANY_EXTEND_VECTOR_INREG, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1107 case ISD::ANY_EXTEND_VECTOR_INREG: { in PreprocessISelDAG()
H A DX86ISelLowering.cpp2358 ISD::ANY_EXTEND_VECTOR_INREG, in X86TargetLowering()
6922 case ISD::ANY_EXTEND_VECTOR_INREG: in getOpcode_EXTEND()
6938 case ISD::ANY_EXTEND_VECTOR_INREG: in getOpcode_EXTEND_VECTOR_INREG()
6939 return ISD::ANY_EXTEND_VECTOR_INREG; in getOpcode_EXTEND_VECTOR_INREG()
8580 case ISD::ANY_EXTEND_VECTOR_INREG: { in getFauxShuffleMask()
8590 (ISD::ANY_EXTEND == Opcode || ISD::ANY_EXTEND_VECTOR_INREG == Opcode); in getFauxShuffleMask()
54517 InOpcode == ISD::ANY_EXTEND_VECTOR_INREG || in combineEXTRACT_SUBVECTOR()
54774 if ((Opcode == ISD::ANY_EXTEND_VECTOR_INREG || in combineEXTEND_VECTOR_INREG()
55106 case ISD::ANY_EXTEND_VECTOR_INREG: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6117 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) && in combineExtract()