Home
last modified time | relevance | path

Searched refs:ring_enc (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0.c221 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_sw_init()
344 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_hw_init()
355 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_hw_init()
1281 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_start()
1314 rb_ptr += ring_enc->ring_size; in vcn_v4_0_init_ring_metadata()
1330 struct amdgpu_ring *ring_enc; in vcn_v4_0_start_sriov() local
1447 ring_enc = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_start_sriov()
1448 ring_enc->wptr = 0; in vcn_v4_0_start_sriov()
1449 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_start_sriov()
1999 adev->vcn.inst[i].ring_enc[0].funcs = in vcn_v4_0_set_unified_ring_funcs()
[all …]
H A Duvd_v7_0.c89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_rptr()
123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_wptr()
161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_set_wptr()
457 ring = &adev->uvd.inst[j].ring_enc[i]; in uvd_v7_0_sw_init()
575 ring = &adev->uvd.inst[j].ring_enc[i]; in uvd_v7_0_hw_init()
762 adev->uvd.inst[i].ring_enc[0].wptr = 0; in uvd_v7_0_mmsch_start()
763 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; in uvd_v7_0_mmsch_start()
921 ring = &adev->uvd.inst[i].ring_enc[0]; in uvd_v7_0_sriov_start()
1115 ring = &adev->uvd.inst[k].ring_enc[0]; in uvd_v7_0_start()
1122 ring = &adev->uvd.inst[k].ring_enc[1]; in uvd_v7_0_start()
[all …]
H A Dvcn_v5_0_1.c127 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v5_0_1_sw_init()
144 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); in vcn_v5_0_1_sw_init()
211 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v5_0_1_hw_init()
635 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v5_0_1_start_dpg_mode()
783 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v5_0_1_start()
935 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v5_0_1_unified_ring_get_rptr()
952 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v5_0_1_unified_ring_get_wptr()
972 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v5_0_1_unified_ring_set_wptr()
1026 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs; in vcn_v5_0_1_set_unified_ring_funcs()
1027 adev->vcn.inst[i].ring_enc[0].me = i; in vcn_v5_0_1_set_unified_ring_funcs()
[all …]
H A Dvcn_v4_0_3.c186 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_3_sw_init()
310 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_3_hw_init()
326 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_3_hw_init()
936 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v4_0_3_start_dpg_mode()
972 struct amdgpu_ring *ring_enc; in vcn_v4_0_3_start_sriov() local
1079 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; in vcn_v4_0_3_start_sriov()
1080 ring_enc->wptr = 0; in vcn_v4_0_3_start_sriov()
1081 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_3_start_sriov()
1086 rb_setup->rb_size = ring_enc->ring_size / 4; in vcn_v4_0_3_start_sriov()
1297 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_3_start()
[all …]
H A Duvd_v6_0.c95 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_get_rptr()
125 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_get_wptr()
156 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_set_wptr()
404 adev->uvd.inst->ring_enc[i].funcs = NULL; in uvd_v6_0_sw_init()
425 ring = &adev->uvd.inst->ring_enc[i]; in uvd_v6_0_sw_init()
449 amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]); in uvd_v6_0_sw_fini()
506 ring = &adev->uvd.inst->ring_enc[i]; in uvd_v6_0_hw_init()
866 ring = &adev->uvd.inst->ring_enc[0]; in uvd_v6_0_start()
873 ring = &adev->uvd.inst->ring_enc[1]; in uvd_v6_0_start()
1262 amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]); in uvd_v6_0_process_interrupt()
[all …]
H A Dvcn_v2_5.c379 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_sw_init()
493 adev->vcn.inst[j].ring_enc[0].sched.ready = true; in vcn_v2_5_hw_init()
494 adev->vcn.inst[j].ring_enc[1].sched.ready = false; in vcn_v2_5_hw_init()
495 adev->vcn.inst[j].ring_enc[2].sched.ready = false; in vcn_v2_5_hw_init()
509 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_hw_init()
1329 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_start()
1338 ring = &adev->vcn.inst[i].ring_enc[1]; in vcn_v2_5_start()
1498 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_sriov_start()
1684 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v2_5_pause_dpg_mode()
1694 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; in vcn_v2_5_pause_dpg_mode()
[all …]
H A Dvcn_v5_0_0.c176 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v5_0_0_sw_init()
201 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); in vcn_v5_0_0_sw_init()
275 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v5_0_0_hw_init()
771 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v5_0_0_start_dpg_mode()
924 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v5_0_0_start()
1127 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v5_0_0_unified_ring_get_rptr()
1144 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v5_0_0_unified_ring_get_wptr()
1164 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v5_0_0_unified_ring_set_wptr()
1219 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs; in vcn_v5_0_0_set_unified_ring_funcs()
1220 adev->vcn.inst[i].ring_enc[0].me = i; in vcn_v5_0_0_set_unified_ring_funcs()
[all …]
H A Dvcn_v2_0.c201 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_sw_init()
298 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_hw_init()
1138 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_start()
1147 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_start()
1295 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_pause_dpg_mode()
1305 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_pause_dpg_mode()
1612 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v2_0_enc_ring_get_rptr()
1629 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_get_wptr()
1884 adev->vcn.inst->ring_enc[i].wptr = 0; in vcn_v2_0_start_mmsch()
1885 adev->vcn.inst->ring_enc[i].wptr_old = 0; in vcn_v2_0_start_mmsch()
[all …]
H A Dvcn_v1_0.c184 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v1_0_sw_init()
258 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v1_0_hw_init()
996 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v1_0_start_spg_mode()
1003 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v1_0_start_spg_mode()
1306 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v1_0_pause_dpg_mode()
1313 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v1_0_pause_dpg_mode()
1653 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_get_rptr()
1670 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_get_wptr()
1687 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_set_wptr()
1796 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); in vcn_v1_0_process_interrupt()
[all …]
H A Dvcn_v3_0.c260 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_sw_init()
391 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_hw_init()
419 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_hw_init()
1345 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v3_0_start()
1354 ring = &adev->vcn.inst[i].ring_enc[1]; in vcn_v3_0_start()
1476 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_start_sriov()
1725 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v3_0_pause_dpg_mode()
1735 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; in vcn_v3_0_pause_dpg_mode()
2029 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v3_0_enc_ring_get_rptr()
2046 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v3_0_enc_ring_get_wptr()
[all …]
H A Dvcn_v4_0_5.c184 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_5_sw_init()
297 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_5_hw_init()
1000 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v4_0_5_start_dpg_mode()
1187 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_5_start()
1399 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v4_0_5_unified_ring_get_rptr()
1416 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v4_0_5_unified_ring_get_wptr()
1436 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v4_0_5_unified_ring_set_wptr()
1494 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs; in vcn_v4_0_5_set_unified_ring_funcs()
1495 adev->vcn.inst[i].ring_enc[0].me = i; in vcn_v4_0_5_set_unified_ring_funcs()
1628 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); in vcn_v4_0_5_process_interrupt()
H A Damdgpu_uvd.h46 struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS]; member
H A Damdgpu_vcn.c279 amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]); in amdgpu_vcn_sw_fini()
420 fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[j]); in amdgpu_vcn_idle_work_handler()
499 fences += amdgpu_fence_count_emitted(&vcn_inst->ring_enc[i]); in amdgpu_vcn_ring_begin_use()
1383 ring = &adev->vcn.inst[i].ring_enc[0]; in amdgpu_debugfs_vcn_sched_mask_set()
1404 ring = &adev->vcn.inst[i].ring_enc[0]; in amdgpu_debugfs_vcn_sched_mask_get()
H A Damdgpu_vcn.h304 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; member
H A Damdgpu_uvd.c389 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); in amdgpu_uvd_sw_fini()
1272 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); in amdgpu_uvd_idle_work_handler()
H A Djpeg_v1_0.c616 if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_enc[cnt])) in jpeg_v1_0_ring_begin_use()
H A Damdgpu_kms.c438 if (adev->uvd.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()
463 if (adev->vcn.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()