drm/amdgpu: move UVD and VCE sched entity init after sched init

We need kernel scheduling entities to deal with handle clean up
if apps are not cleaned up properly. With commit 56e449603f0ac5
("drm

drm/amdgpu: move UVD and VCE sched entity init after sched init

We need kernel scheduling entities to deal with handle clean up
if apps are not cleaned up properly. With commit 56e449603f0ac5
("drm/sched: Convert the GPU scheduler to variable number of run-queues")
the scheduler entities have to be created after scheduler init, so
change the ordering to fix this.

v2: Leave logic in UVD and VCE code

Fixes: 56e449603f0a ("drm/sched: Convert the GPU scheduler to variable number of run-queues")
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Luben Tuikov <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]

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drm/amd: Split up UVD suspend into prepare and suspend steps

amdgpu_uvd_suspend() allocates memory and copies objects into that
allocated memory. This fails under memory pressure. Instead move
maj

drm/amd: Split up UVD suspend into prepare and suspend steps

amdgpu_uvd_suspend() allocates memory and copies objects into that
allocated memory. This fails under memory pressure. Instead move
majority of this code into a prepare step when swap can still be
allocated.

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Mario Limonciello <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: use job and ib structures directly in CS parsers

Instead of providing the ib index provide the job and ib pointers directly to
the patch and parse functions for UVD and VCE.

Also move t

drm/amdgpu: use job and ib structures directly in CS parsers

Instead of providing the ib index provide the job and ib pointers directly to
the patch and parse functions for UVD and VCE.

Also move the set/get functions for IB values to the IB declerations.

Signed-off-by: Christian König <[email protected]>
Acked-by: Andrey Grodzovsky <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: UVD avoid memory allocation during IB test

move BO allocation in sw_init.

Signed-off-by: xinhui pan <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-o

drm/amdgpu: UVD avoid memory allocation during IB test

move BO allocation in sw_init.

Signed-off-by: xinhui pan <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: fix SI UVD firmware validate resume fail

The SI UVD firmware validate key is stored at the end of firmware,
which is changed during resume while playing video. So get the key
at sw_init

drm/amdgpu: fix SI UVD firmware validate resume fail

The SI UVD firmware validate key is stored at the end of firmware,
which is changed during resume while playing video. So get the key
at sw_init and store it for fw validate using.

Signed-off-by: Sonny Jiang <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]

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drm/amdgpu: fix SI UVD firmware validate resume fail

The SI UVD firmware validate key is stored at the end of firmware,
which is changed during resume while playing video. So get the key
at sw_init

drm/amdgpu: fix SI UVD firmware validate resume fail

The SI UVD firmware validate key is stored at the end of firmware,
which is changed during resume while playing video. So get the key
at sw_init and store it for fw validate using.

Signed-off-by: Sonny Jiang <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd:Enable/Disable NBPSTATE on On/OFF of UVD

We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
In this patch

drm/amd:Enable/Disable NBPSTATE on On/OFF of UVD

We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
In this patch ,disabling low memory P state only when video
size >= 4k.
Multiple runs of power measurement shows no impact

Signed-off-by: suresh guttula <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/uvd: UVD entity initialization relys on ring initialization

Entity init should after ring init, as the entity's sched_rq's initialization
is in ring init.

SWDEV-161495

Signed-off-by: Em

drm/amdgpu/uvd: UVD entity initialization relys on ring initialization

Entity init should after ring init, as the entity's sched_rq's initialization
is in ring init.

SWDEV-161495

Signed-off-by: Emily Deng <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: implement harvesting support for UVD 7.2 (v3)

Properly handle cases where one or more instance of the IP
block may be harvested.

v2: make sure ip_num_rings is initialized amdgpu_queue_m

drm/amdgpu: implement harvesting support for UVD 7.2 (v3)

Properly handle cases where one or more instance of the IP
block may be harvested.

v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c
v3: rebase on Christian's UVD changes, drop unused var

Reviewed-by: James Zhu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: clean up UVD instance handling v2

The whole handle, filp and entity handling is superfluous here.

We should have reviewed that more thoughtfully. It looks like somebody
just made the co

drm/amdgpu: clean up UVD instance handling v2

The whole handle, filp and entity handling is superfluous here.

We should have reviewed that more thoughtfully. It looks like somebody
just made the code instance aware without knowing the background.

v2: fix one more missed case in amdgpu_uvd_suspend

Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Christian König <[email protected]>
Acked-by: Chunming Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: remove superflous UVD encode entity

Not sure what that was every used for, but now it is completely unused.

Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Christian König <christ

drm/amdgpu: remove superflous UVD encode entity

Not sure what that was every used for, but now it is completely unused.

Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Christian König <[email protected]>
Acked-by: Chunming Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu:All UVD instances share one idle_work handle

All UVD instanses have only one dpm control, so it is better
to share one idle_work handle.

Signed-off-by: James Zhu <[email protected]>
Revi

drm/amdgpu:All UVD instances share one idle_work handle

All UVD instanses have only one dpm control, so it is better
to share one idle_work handle.

Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Tested-by: Stefan Agner <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/vg20:Restruct uvd to support multiple uvds

Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support
multiple uvds. There are no any logical changes here.

Signed-off-by: James Zhu

drm/amdgpu/vg20:Restruct uvd to support multiple uvds

Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support
multiple uvds. There are no any logical changes here.

Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm: move amd_gpu_scheduler into common location

This moves and renames the AMDGPU scheduler to a common location in DRM
in order to facilitate re-use by other drivers. This is mostly a straight
for

drm: move amd_gpu_scheduler into common location

This moves and renames the AMDGPU scheduler to a common location in DRM
in order to facilitate re-use by other drivers. This is mostly a straight
forward rename with no code changes.

One notable exception is the function to_drm_sched_fence(), which is no
longer a inline header function to avoid the need to export the
drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures.

Reviewed-by: Chunming Zhou <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/amdgpu: fix UVD mc offsets

When UVD bo is created, its size is based on the information from firmware
header (ucode_size_bytes). The same value should be be used when programming
UVD mc cont

drm/amd/amdgpu: fix UVD mc offsets

When UVD bo is created, its size is based on the information from firmware
header (ucode_size_bytes). The same value should be be used when programming
UVD mc controller offsets, otherwise it can happen that
(mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point
AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.

Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register,
AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't,
(mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point
AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.

v2: move firmware size calculation into macro definition
v3: align firmware size to the gpu page size

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Piotr Redlewski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add uvd enc run queue

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by

drm/amdgpu: add uvd enc run queue

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add uvd enc rings

And initialize them

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]

drm/amdgpu: add uvd enc rings

And initialize them

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: move amdgpu_uvd structure to uvd header

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <alexander.deucher@amd.

drm/amdgpu: move amdgpu_uvd structure to uvd header

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amd/amdgpu: get maximum and used UVD handles (v4)

Change History
--------------

v4: Changes suggested by Emil, Christian
- return -ENODATA for asics with unlimited sessions

v3: changes suggest

drm/amd/amdgpu: get maximum and used UVD handles (v4)

Change History
--------------

v4: Changes suggested by Emil, Christian
- return -ENODATA for asics with unlimited sessions

v3: changes suggested by Christian
- Add a check for UVD IP block using AMDGPU_HW_IP_UVD
query type.
- Add a check for asic_type to be less than
CHIP_POLARIS10 since starting Polaris, we support
unlimited UVD instances.
- Add kerneldoc style comment for
amdgpu_uvd_used_handles().

v2: as suggested by Christian
- Add a new query AMDGPU_INFO_NUM_HANDLES
- Create a helper function to return the number
of currently used UVD handles.
- Modify the logic to count the number of used
UVD handles since handles can be freed in
non-linear fashion.

v1:
- User might want to query the maximum number of UVD
instances supported by firmware. In addition to that,
if there are multiple applications using UVD handles
at the same time, he might also want to query the
currently used number of handles.

For this we add two variables max_handles and
used_handles inside drm_amdgpu_info_hw_ip. So now
an application (or libdrm) can use AMDGPU_INFO IOCTL
with AMDGPU_INFO_HW_IP_INFO query type to get these
values.

Signed-off-by: Arindam Nath <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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dma-buf: Rename struct fence to dma_fence

I plan to usurp the short name of struct fence for a core kernel struct,
and so I need to rename the specialised fence/timeline for DMA
operations to make r

dma-buf: Rename struct fence to dma_fence

I plan to usurp the short name of struct fence for a core kernel struct,
and so I need to rename the specialised fence/timeline for DMA
operations to make room.

A consensus was reached in
https://lists.freedesktop.org/archives/dri-devel/2016-July/113083.html
that making clear this fence applies to DMA operations was a good thing.
Since then the patch has grown a bit as usage increases, so hopefully it
remains a good thing!

(v2...: rebase, rerun spatch)
v3: Compile on msm, spotted a manual fixup that I broke.
v4: Try again for msm, sorry Daniel

coccinelle script:
@@

@@
- struct fence
+ struct dma_fence
@@

@@
- struct fence_ops
+ struct dma_fence_ops
@@

@@
- struct fence_cb
+ struct dma_fence_cb
@@

@@
- struct fence_array
+ struct dma_fence_array
@@

@@
- enum fence_flag_bits
+ enum dma_fence_flag_bits
@@

@@
(
- fence_init
+ dma_fence_init
|
- fence_release
+ dma_fence_release
|
- fence_free
+ dma_fence_free
|
- fence_get
+ dma_fence_get
|
- fence_get_rcu
+ dma_fence_get_rcu
|
- fence_put
+ dma_fence_put
|
- fence_signal
+ dma_fence_signal
|
- fence_signal_locked
+ dma_fence_signal_locked
|
- fence_default_wait
+ dma_fence_default_wait
|
- fence_add_callback
+ dma_fence_add_callback
|
- fence_remove_callback
+ dma_fence_remove_callback
|
- fence_enable_sw_signaling
+ dma_fence_enable_sw_signaling
|
- fence_is_signaled_locked
+ dma_fence_is_signaled_locked
|
- fence_is_signaled
+ dma_fence_is_signaled
|
- fence_is_later
+ dma_fence_is_later
|
- fence_later
+ dma_fence_later
|
- fence_wait_timeout
+ dma_fence_wait_timeout
|
- fence_wait_any_timeout
+ dma_fence_wait_any_timeout
|
- fence_wait
+ dma_fence_wait
|
- fence_context_alloc
+ dma_fence_context_alloc
|
- fence_array_create
+ dma_fence_array_create
|
- to_fence_array
+ to_dma_fence_array
|
- fence_is_array
+ dma_fence_is_array
|
- trace_fence_emit
+ trace_dma_fence_emit
|
- FENCE_TRACE
+ DMA_FENCE_TRACE
|
- FENCE_WARN
+ DMA_FENCE_WARN
|
- FENCE_ERR
+ DMA_FENCE_ERR
)
(
...
)

Signed-off-by: Chris Wilson <[email protected]>
Reviewed-by: Gustavo Padovan <[email protected]>
Acked-by: Sumit Semwal <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]

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drm/amdgpu: add a fence timeout for the IB tests v2

10ms should be enough for now.

v2: fix some typos in CIK code

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Chunming Zh

drm/amdgpu: add a fence timeout for the IB tests v2

10ms should be enough for now.

v2: fix some typos in CIK code

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
Reviewed-by: Edward O'Callaghan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: move UVD IB test into common code v2

Since we now raise the clocks from begin_use() we don't need
a separate function for each hw generation any more.

v2: remove unintentional lowering

drm/amdgpu: move UVD IB test into common code v2

Since we now raise the clocks from begin_use() we don't need
a separate function for each hw generation any more.

v2: remove unintentional lowering of the UVD clocks, fix typos for CIK hw.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Edward O'Callaghan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: use begin/end_use for UVD power/clock gating

This fixes turning power and clock on when it is actually needed.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Edw

drm/amdgpu: use begin/end_use for UVD power/clock gating

This fixes turning power and clock on when it is actually needed.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Edward O'Callaghan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: send UVD IB tests directly to the ring again

We need the IB test for GPU resets as well and
the scheduler should be stoped then.

Signed-off-by: Christian König <[email protected]

drm/amdgpu: send UVD IB tests directly to the ring again

We need the IB test for GPU resets as well and
the scheduler should be stoped then.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: change uvd ib test to use kernel fence directly

Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian K?nig <[email protected]>
Reviewed-by: Jammy Zhou <jammy.

drm/amdgpu: change uvd ib test to use kernel fence directly

Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian K?nig <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>

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