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Searched refs:WREG32_NO_KIQ (Results 1 – 18 of 18) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_ai.c144 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
146 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg()
148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
150 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg()
247 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq()
305 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_rcv_irq()
H A Dmxgpu_nv.c148 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req); in xgpu_nv_mailbox_trans_msg()
149 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1); in xgpu_nv_mailbox_trans_msg()
150 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2); in xgpu_nv_mailbox_trans_msg()
151 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW3, data3); in xgpu_nv_mailbox_trans_msg()
293 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_nv_set_mailbox_ack_irq()
357 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_nv_set_mailbox_rcv_irq()
H A Dmxgpu_vi.c327 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
350 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
361 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg); in xgpu_vi_mailbox_trans_msg()
508 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_ack_irq()
541 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_rcv_irq()
H A Dvega20_ih.c126 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega20_ih_toggle_ring_interrupts()
135 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega20_ih_toggle_ring_interrupts()
453 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega20_ih_get_wptr()
459 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega20_ih_get_wptr()
H A Dih_v6_0.c148 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_toggle_ring_interrupts()
157 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_toggle_ring_interrupts()
463 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_get_wptr()
469 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_get_wptr()
H A Dhdp_v5_2.c34 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, in hdp_v5_2_flush_hdp()
H A Dvi.c304 WREG32_NO_KIQ(mmPCIE_INDEX, reg); in vi_pcie_rreg()
316 WREG32_NO_KIQ(mmPCIE_INDEX, reg); in vi_pcie_wreg()
318 WREG32_NO_KIQ(mmPCIE_DATA, v); in vi_pcie_wreg()
329 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); in vi_smc_rreg()
340 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); in vi_smc_wreg()
341 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); in vi_smc_wreg()
H A Dvega10_ih.c373 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega10_ih_get_wptr()
379 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega10_ih_get_wptr()
H A Dnavi10_ih.c443 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in navi10_ih_get_wptr()
449 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in navi10_ih_get_wptr()
H A Dih_v6_1.c435 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_1_get_wptr()
441 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_1_get_wptr()
H A Dih_v7_0.c435 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v7_0_get_wptr()
441 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v7_0_get_wptr()
H A Damdgpu_display.c1815 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t) cursor.start) | 0x80000000); in amdgpu_display_set_pixel()
1817 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); in amdgpu_display_set_pixel()
1818 WREG32_NO_KIQ(mmMM_DATA, color); in amdgpu_display_set_pixel()
H A Dgmc_v12_0.c270 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); in gmc_v12_0_flush_vm_hub()
H A Dgmc_v11_0.c293 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); in gmc_v11_0_flush_gpu_tlb()
H A Damdgpu_virt.c1161 WREG32_NO_KIQ(offset, value); in amdgpu_sriov_wreg()
H A Damdgpu.h1319 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) macro
H A Damdgpu_device.c590 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); in amdgpu_device_mm_access()
592 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); in amdgpu_device_mm_access()
596 WREG32_NO_KIQ(mmMM_DATA, *data++); in amdgpu_device_mm_access()
H A Dgfx_v8_0.c5580 WREG32_NO_KIQ(mmRLC_SPM_VMID, data); in gfx_v8_0_update_spm_vmid()