| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 687 .addReg(SrcReg) in expand()
795 .addReg(SrcReg) in expand()
820 .addReg(SrcReg) in expand()
1162 .addReg(DstReg, in expand()
1688 .addReg(DstLoReg); in expandLSLW8Rd()
1715 .addReg(DstLoReg); in expandLSLW12Rd()
1886 .addReg(DstHiReg); in expandLSRW8Rd()
1913 .addReg(DstHiReg); in expandLSRW12Rd()
2049 .addReg(DstHiReg); in expandASRW7Rd()
2085 .addReg(DstHiReg); in expandASRW8Rd()
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| H A D | AVRFrameLowering.cpp | 71 .addReg(STI.getTmpRegister(), RegState::Kill) in emitPrologue()
78 .addReg(STI.getTmpRegister(), RegState::Kill) in emitPrologue()
82 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
86 .addReg(STI.getZeroRegister(), RegState::Kill) in emitPrologue()
109 .addReg(AVR::SP) in emitPrologue()
134 .addReg(AVR::R29R28) in emitPrologue()
157 .addReg(STI.getTmpRegister(), RegState::Kill); in restoreStatusRegister()
221 .addReg(AVR::R29R28, RegState::Kill); in emitEpilogue()
283 .addReg(Reg, getKillRegState(IsNotLiveIn)) in spillCalleeSavedRegisters()
377 .addReg(AVR::R31R30, RegState::Kill) in eliminateCallFramePseudoInstr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 164 .addReg(AddrReg) in doAtomicBinOpExpansion()
211 .addReg(AddrReg) in doAtomicBinOpExpansion()
232 .addReg(MaskReg); in insertMaskedMerge()
258 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
293 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
342 .addReg(ValReg) in insertSext()
345 .addReg(ValReg) in insertSext()
394 .addReg(AddrReg) in expandAtomicMinMaxOp()
397 .addReg(DestReg) in expandAtomicMinMaxOp()
400 .addReg(DestReg) in expandAtomicMinMaxOp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB); in expandAtomicCmpSwapSubword()
165 .addReg(Ptr) in expandAtomicCmpSwapSubword()
169 .addReg(ZERO) in expandAtomicCmpSwapSubword()
280 .addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB); in expandAtomicCmpSwap()
288 .addReg(Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwap()
534 .addReg(OldVal).addReg(Mask2); in expandAtomicBinOpSubword()
536 .addReg(StoreVal).addReg(BinOpRes); in expandAtomicBinOpSubword()
538 .addReg(StoreVal).addReg(Ptr).addImm(0); in expandAtomicBinOpSubword()
540 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB); in expandAtomicBinOpSubword()
550 .addReg(OldVal).addReg(Mask); in expandAtomicBinOpSubword()
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| H A D | MipsFastISel.cpp | 328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
649 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
667 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
673 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
1060 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
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| H A D | MipsBranchExpansion.cpp | 352 MIB.addReg(MO.getReg()); in replaceBranch()
471 .addReg(Mips::SP) in expandToLongBranch()
474 .addReg(Mips::RA) in expandToLongBranch()
475 .addReg(Mips::SP) in expandToLongBranch()
517 .addReg(Mips::RA) in expandToLongBranch()
518 .addReg(Mips::AT); in expandToLongBranch()
520 .addReg(Mips::SP) in expandToLongBranch()
532 .addReg(Mips::SP) in expandToLongBranch()
594 .addReg(Mips::SP_64) in expandToLongBranch()
716 .addReg(Mips::AT) in expandToLongBranch()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCExpandAtomicPseudoInsts.cpp | 59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
204 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicRMW128()
263 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
[all …]
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| H A D | PPCFrameLowering.cpp | 877 .addReg(SPReg); in emitPrologue()
893 .addReg(SPReg) in emitPrologue()
894 .addReg(SPReg); in emitPrologue()
983 .addReg(SPReg); in emitPrologue()
1163 .addReg(SPReg) in emitPrologue()
1164 .addReg(SPReg); in emitPrologue()
1785 .addReg(SPReg); in emitEpilogue()
1799 .addReg(RBReg); in emitEpilogue()
1807 .addReg(RBReg); in emitEpilogue()
1826 .addReg(RBReg); in emitEpilogue()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 185 .addReg(0)); in runOnMachineFunction()
1501 .addReg(0) in emitInstruction()
1503 .addReg(0)); in emitInstruction()
1547 .addReg(0) in emitInstruction()
1556 .addReg(0) in emitInstruction()
1567 .addReg(0) in emitInstruction()
1991 .addReg(0) in emitInstruction()
2114 .addReg(0) in emitInstruction()
2131 .addReg(0) in emitInstruction()
2141 .addReg(0) in emitInstruction()
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| H A D | ARMExpandPseudoInsts.cpp | 859 MIB.addReg(D0); in ExpandVTBL()
1351 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1425 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1665 .addReg(Reg) in CMSERestoreFPRegsV8()
1671 .addReg(Reg) in CMSERestoreFPRegsV8()
1732 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1843 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1866 .addReg(NewReg) in ExpandCMP_SWAP()
1867 .addReg(AddrReg); in ExpandCMP_SWAP()
2037 PushMIB.addReg( in CMSEPushCalleeSaves()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 278 .addReg(AddrReg); in doAtomicBinOpExpansion()
292 .addReg(AddrReg) in doAtomicBinOpExpansion()
316 .addReg(MaskReg); in insertMaskedMerge()
347 .addReg(AddrReg); in doMaskedAtomicBinOpExpansion()
380 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
431 .addReg(ValReg) in insertSext()
434 .addReg(ValReg) in insertSext()
488 .addReg(AddrReg); in expandAtomicMinMaxOp()
490 .addReg(DestReg) in expandAtomicMinMaxOp()
493 .addReg(DestReg) in expandAtomicMinMaxOp()
[all …]
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| H A D | RISCVAsmPrinter.cpp | 598 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8), in EmitHwasanMemaccessSymbols()
612 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0), in EmitHwasanMemaccessSymbols()
616 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56), in EmitHwasanMemaccessSymbols()
622 .addReg(RISCV::X7) in EmitHwasanMemaccessSymbols()
623 .addReg(RISCV::X6) in EmitHwasanMemaccessSymbols()
644 .addReg(RISCV::X6) in EmitHwasanMemaccessSymbols()
650 MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols()
667 MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols()
670 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0), in EmitHwasanMemaccessSymbols()
737 MCInstBuilder(RISCV::SD).addReg(RISCV::X8).addReg(RISCV::X2).addImm(8 * in EmitHwasanMemaccessSymbols()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 209 .addReg(SystemZ::R7D) in emitInstruction()
211 .addReg(0); in emitInstruction()
225 .addReg(SystemZ::R7D) in emitInstruction()
227 .addReg(0); in emitInstruction()
235 .addReg(SystemZ::R14D) in emitInstruction()
244 .addReg(SystemZ::R14D) in emitInstruction()
253 .addReg(SystemZ::R14D) in emitInstruction()
262 .addReg(SystemZ::R14D) in emitInstruction()
271 .addReg(SystemZ::R14D) in emitInstruction()
566 .addReg(0).addImm(0); in emitInstruction()
[all …]
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| H A D | SystemZFrameLowering.cpp | 637 .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D); in emitPrologue()
642 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D) in emitPrologue()
786 .addReg(SystemZ::R15D).addImm(Size - 8).addReg(0) in inlineStackProbe()
793 .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D); in inlineStackProbe()
823 .addReg(SystemZ::R15D).addReg(SystemZ::R0D); in inlineStackProbe()
837 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D) in inlineStackProbe()
1174 .addReg(0); in restoreCalleeSavedRegisters()
1371 .addReg(0); in inlineStackProbe()
1396 .addReg(0) in inlineStackProbe()
1398 .addReg(0); in inlineStackProbe()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 624 .addReg(AArch64::W16) in emitHwasanMemaccessSymbols()
626 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
632 .addReg(AArch64::XZR) in emitHwasanMemaccessSymbols()
633 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
634 .addReg(Reg) in emitHwasanMemaccessSymbols()
686 .addReg(AArch64::X17) in emitHwasanMemaccessSymbols()
687 .addReg(Reg) in emitHwasanMemaccessSymbols()
711 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
712 .addReg(Reg) in emitHwasanMemaccessSymbols()
724 .addReg(Reg) in emitHwasanMemaccessSymbols()
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| H A D | AArch64SIMDInstrOpt.cpp | 567 .addReg(StReg[0]) in optimizeLdStInterleave()
568 .addReg(StReg[1]); in optimizeLdStInterleave()
574 .addReg(ZipDest[0]) in optimizeLdStInterleave()
575 .addReg(ZipDest[1]) in optimizeLdStInterleave()
576 .addReg(AddrReg) in optimizeLdStInterleave()
589 .addReg(StReg[0]) in optimizeLdStInterleave()
590 .addReg(StReg[2]); in optimizeLdStInterleave()
595 .addReg(StReg[1]) in optimizeLdStInterleave()
596 .addReg(StReg[3]); in optimizeLdStInterleave()
616 .addReg(AddrReg) in optimizeLdStInterleave()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
177 MIB.addReg(AM.Base.Reg); in addFullAddress()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
189 return MIB.addReg(0); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEFrameLowering.cpp | 153 .addReg(VE::SX11) in emitPrologueInsns()
156 .addReg(VE::SX9); in emitPrologueInsns()
158 .addReg(VE::SX11) in emitPrologueInsns()
165 .addReg(VE::SX11) in emitPrologueInsns()
170 .addReg(VE::SX11) in emitPrologueInsns()
177 .addReg(VE::SX11) in emitPrologueInsns()
201 .addReg(VE::SX11) in emitEpilogueInsns()
206 .addReg(VE::SX11) in emitEpilogueInsns()
210 .addReg(VE::SX11) in emitEpilogueInsns()
216 .addReg(VE::SX11) in emitEpilogueInsns()
[all …]
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| H A D | VERegisterInfo.cpp | 216 .addReg(clobber) in prepareReplaceFI()
217 .addReg(FrameReg) in prepareReplaceFI()
248 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg); in processSTQ()
304 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM()
357 .addReg(DestReg); in processLDVM()
362 .addReg(DestReg); in processLDVM()
386 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM512()
397 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM512()
434 .addReg(DestLoReg); in processLDVM512()
444 .addReg(DestHiReg); in processLDVM512()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 71 .addReg(FrameReg) in InsertFPImmInst()
78 .addReg(FrameReg) in InsertFPImmInst()
84 .addReg(FrameReg) in InsertFPImmInst()
108 .addReg(FrameReg) in InsertFPConstInst()
109 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
115 .addReg(FrameReg) in InsertFPConstInst()
116 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
121 .addReg(FrameReg) in InsertFPConstInst()
187 .addReg(ScratchBase, RegState::Kill) in InsertSPConstInst()
194 .addReg(ScratchBase, RegState::Kill) in InsertSPConstInst()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.cpp | 250 .addReg(DstReg) in movImm()
266 .addReg(DstReg) in movImm()
271 .addReg(DstReg) in movImm()
279 .addReg(DstReg) in movImm()
284 .addReg(DstReg) in movImm()
288 .addReg(DstReg) in movImm()
301 .addReg(DstReg) in movImm()
310 .addReg(DstReg) in movImm()
319 .addReg(DstReg) in movImm()
515 .addReg(DestReg) in copyPhysReg()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 658 .addReg(P.first); in splitMemRef()
662 .addReg(P.second); in splitMemRef()
674 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
808 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
848 .addReg(TmpR) in splitShift()
858 .addReg(TmpR) in splitShift()
944 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
959 .addReg(TmpR1); in splitAslOr()
961 .addReg(TmpR2) in splitAslOr()
1113 .addReg(Pr.first) in collapseRegPairs()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 407 .addReg(DstLo) in selectG_ADD_SUB()
409 .addReg(DstHi) in selectG_ADD_SUB()
903 .addReg(M0Val); in selectInterpP1F16()
1623 .addReg(M0Val); in selectDSOrderedIntrinsic()
2706 .addReg(HiReg) in selectG_FNEG()
2710 .addReg(LoReg) in selectG_FNEG()
2712 .addReg(OpReg) in selectG_FNEG()
2748 .addReg(HiReg) in selectG_FABS()
2752 .addReg(LoReg) in selectG_FABS()
2754 .addReg(OpReg) in selectG_FABS()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 261 .addReg(ImpDefReg) in selectZExt()
262 .addReg(SrcReg) in selectZExt()
267 .addReg(NewDefReg) in selectZExt()
331 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
348 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
379 .addReg(TmpReg, RegState::Kill) in selectI64ImmDirect()
557 .addReg(Tmp2Reg) in selectI64ImmDirect()
683 .addReg(TOCReg) in selectConstantPool()
688 .addReg(TOCReg) in selectConstantPool()
695 .addReg(HaAddrReg) in selectConstantPool()
[all …]
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