Lines Matching refs:addReg
590 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
594 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
596 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
598 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
600 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
662 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
723 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
725 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
727 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
729 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
738 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
782 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
784 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
786 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
788 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
809 MIB.addReg(D0, SrcFlags); in ExpandLaneOp()
811 MIB.addReg(D1, SrcFlags); in ExpandLaneOp()
813 MIB.addReg(D2, SrcFlags); in ExpandLaneOp()
815 MIB.addReg(D3, SrcFlags); in ExpandLaneOp()
830 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
859 MIB.addReg(D0); in ExpandVTBL()
870 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); in ExpandVTBL()
893 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags); in ExpandMQQPRLoadStore()
894 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags); in ExpandMQQPRLoadStore()
895 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags); in ExpandMQQPRLoadStore()
896 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags); in ExpandMQQPRLoadStore()
899 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags); in ExpandMQQPRLoadStore()
900 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags); in ExpandMQQPRLoadStore()
901 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags); in ExpandMQQPRLoadStore()
902 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags); in ExpandMQQPRLoadStore()
906 MIB.addReg(SrcReg, RegState::Implicit); in ExpandMQQPRLoadStore()
1027 .addReg(DstReg) in ExpandTMOV32BitImm()
1042 MIB.addReg(DstReg); in ExpandTMOV32BitImm()
1088 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1089 .addReg(DstReg); in ExpandMOV32BitImm()
1095 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1096 .addReg(DstReg); in ExpandMOV32BitImm()
1109 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1110 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1134 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
1143 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1144 .addReg(DstReg); in ExpandMOV32BitImm()
1148 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
1190 CLRM.addReg(R, RegState::Define); in CMSEClearGPRegs()
1191 CLRM.addReg(ARM::APSR, RegState::Define); in CMSEClearGPRegs()
1192 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1200 .addReg(ClobberReg) in CMSEClearGPRegs()
1206 .addReg(ClobberReg) in CMSEClearGPRegs()
1309 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1316 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1325 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1326 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1333 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1340 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1351 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1356 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1361 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1387 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1388 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1398 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1399 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1425 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1446 .addReg(SaveReg1, RegState::Define) in CMSESaveClearFPRegsV8()
1447 .addReg(SaveReg2, RegState::Define) in CMSESaveClearFPRegsV8()
1448 .addReg(Reg) in CMSESaveClearFPRegsV8()
1460 .addReg(Reg) in CMSESaveClearFPRegsV8()
1477 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1481 VLSTM.addReg(R, RegState::Implicit | in CMSESaveClearFPRegsV8()
1490 .addReg(SaveReg1) in CMSESaveClearFPRegsV8()
1491 .addReg(SaveReg2) in CMSESaveClearFPRegsV8()
1495 .addReg(SaveReg1) in CMSESaveClearFPRegsV8()
1503 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1511 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1515 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1521 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1530 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1534 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1539 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1544 .addReg(SpareReg) in CMSESaveClearFPRegsV8()
1565 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1571 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1575 VLSTM.addReg(R, RegState::Implicit | in CMSESaveClearFPRegsV81()
1581 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1584 VPUSH.addReg(Reg); in CMSESaveClearFPRegsV81()
1591 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1633 .addReg(SaveReg1, RegState::Define) in CMSERestoreFPRegsV8()
1634 .addReg(SaveReg2, RegState::Define) in CMSERestoreFPRegsV8()
1635 .addReg(Reg) in CMSERestoreFPRegsV8()
1647 .addReg(Reg) in CMSERestoreFPRegsV8()
1665 .addReg(Reg) in CMSERestoreFPRegsV8()
1666 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1671 .addReg(Reg) in CMSERestoreFPRegsV8()
1672 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1680 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1687 .addReg(ScratchReg, RegState::Define) in CMSERestoreFPRegsV8()
1692 .addReg(ScratchReg) in CMSERestoreFPRegsV8()
1705 .addReg(ARM::S0, RegState::Define) in CMSERestoreFPRegsV8()
1706 .addReg(ARM::S0, RegState::Undef) in CMSERestoreFPRegsV8()
1721 .addReg(SaveReg1) in CMSERestoreFPRegsV8()
1722 .addReg(SaveReg2) in CMSERestoreFPRegsV8()
1726 .addReg(SaveReg1) in CMSERestoreFPRegsV8()
1732 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1757 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
1762 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1767 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1774 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1781 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1784 VPOP.addReg(Reg, RegState::Define); in CMSERestoreFPRegsV81()
1830 .addReg(DesiredReg, RegState::Kill); in ExpandCMP_SWAP()
1843 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1850 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) in ExpandCMP_SWAP()
1851 .addReg(DesiredReg) in ExpandCMP_SWAP()
1857 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1866 .addReg(NewReg) in ExpandCMP_SWAP()
1867 .addReg(AddrReg); in ExpandCMP_SWAP()
1875 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP()
1881 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1916 MIB.addReg(RegLo, Flags); in addExclusiveRegPair()
1917 MIB.addReg(RegHi, Flags); in addExclusiveRegPair()
1919 MIB.addReg(Reg.getReg(), Flags); in addExclusiveRegPair()
1963 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1967 .addReg(DestLo, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
1968 .addReg(DesiredLo) in ExpandCMP_SWAP_64()
1972 .addReg(DestHi, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
1973 .addReg(DesiredHi) in ExpandCMP_SWAP_64()
1974 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1980 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1992 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1996 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP_64()
2002 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2037 PushMIB.addReg( in CMSEPushCalleeSaves()
2052 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2061 PushMIB2.addReg(Reg, RegState::Kill); in CMSEPushCalleeSaves()
2070 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2074 .addReg(LoReg, RegState::Kill); in CMSEPushCalleeSaves()
2079 .addReg(ARM::SP) in CMSEPushCalleeSaves()
2082 PushMIB.addReg( in CMSEPushCalleeSaves()
2097 PopMIB.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2099 .addReg(ARM::R4 + R, RegState::Kill) in CMSEPopCalleeSaves()
2105 PopMIB2.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2109 .addReg(ARM::SP) in CMSEPopCalleeSaves()
2112 PopMIB.addReg(Reg, RegState::Define); in CMSEPopCalleeSaves()
2163 .addReg(DstReg, in ExpandMI()
2172 .addReg(DstReg, in ExpandMI()
2236 .addReg(JumpTarget.getReg(), RegState::Kill); in ExpandMI()
2267 .addReg(ARM::SP) in ExpandMI()
2288 .addReg(ARM::LR) in ExpandMI()
2327 .addReg(JumpReg) in ExpandMI()
2340 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2341 .addReg(JumpReg) in ExpandMI()
2342 .addReg(ScratchReg) in ExpandMI()
2353 .addReg(JumpReg, RegState::Kill); in ExpandMI()
2523 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
2542 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2584 MIB.addReg(Reg, RegState::Kill); in ExpandMI()
2613 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2614 .addReg(DstReg) in ExpandMI()
2672 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2673 .addReg(DstReg) in ExpandMI()
2707 .addReg(DstReg) in ExpandMI()
2714 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2715 .addReg(DstReg).addImm(LabelId); in ExpandMI()
2750 .addReg(ARM::LR) in ExpandMI()
2754 .addReg(ARM::CPSR, RegState::Undef) in ExpandMI()
2779 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2780 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
2783 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
2811 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) in ExpandMI()
2812 .addReg(D1, SrcIsKill ? RegState::Kill : 0); in ExpandMI()
3169 .addReg(Reg); in ExpandMI()
3176 .addReg(ARM::SP, RegState::Define) in ExpandMI()
3177 .addReg(ARM::SP) in ExpandMI()
3179 .addReg(Reg); in ExpandMI()
3213 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
3215 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()