Lines Matching refs:addReg
174 .addReg(SrcReg); in selectCOPY()
180 .addReg(MaskedReg); in selectCOPY()
261 .addReg(Reg, 0, ComposedSubIdx); in getSubOperand64()
399 .addReg(CarryReg, RegState::Kill) in selectG_ADD_SUB()
407 .addReg(DstLo) in selectG_ADD_SUB()
409 .addReg(DstHi) in selectG_ADD_SUB()
447 .addReg(I.getOperand(4).getReg()); in selectG_UADDO_USUBO_UADDE_USUBE()
461 .addReg(AMDGPU::SCC); in selectG_UADDO_USUBO_UADDE_USUBE()
538 .addReg(SrcReg, 0, SubReg); in selectG_EXTRACT()
567 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
611 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
710 .addReg(Src0); in selectG_BUILD_VECTOR()
715 .addReg(Src1) in selectG_BUILD_VECTOR()
717 .addReg(TmpReg); in selectG_BUILD_VECTOR()
760 .addReg(ShiftSrc0) in selectG_BUILD_VECTOR()
847 .addReg(Src0Reg) in selectG_INSERT()
848 .addReg(Src1Reg) in selectG_INSERT()
872 .addReg(SrcReg) in selectG_SBFX_UBFX()
873 .addReg(OffsetReg) in selectG_SBFX_UBFX()
874 .addReg(WidthReg); in selectG_SBFX_UBFX()
903 .addReg(M0Val); in selectInterpP1F16()
911 .addReg(Src0) // $src0 in selectInterpP1F16()
915 .addReg(InterpMov) // $src2 - 2 f16 values selected by high in selectInterpP1F16()
948 MIB.addReg(Val); in selectWritelane()
960 MIB.addReg(LaneSelect); in selectWritelane()
962 MIB.addReg(Val); in selectWritelane()
970 .addReg(LaneSelect); in selectWritelane()
971 MIB.addReg(AMDGPU::M0); in selectWritelane()
975 MIB.addReg(VDstIn); in selectWritelane()
1329 .addReg(AMDGPU::SCC); in selectG_ICMP_or_FCMP()
1396 SelectedMI.addReg(Src0Reg); in selectIntrinsicCmp()
1399 SelectedMI.addReg(Src1Reg); in selectIntrinsicCmp()
1432 .addReg(SrcReg); in selectBallot()
1440 .addReg(SrcReg) in selectBallot()
1442 .addReg(HiReg) in selectBallot()
1468 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(MaskReg); in selectInverseBallot()
1557 .addReg(LiveIn); in selectReturnAddress()
1623 .addReg(M0Val); in selectDSOrderedIntrinsic()
1629 .addReg(ValReg) in selectDSOrderedIntrinsic()
1721 .addReg(BaseOffset) in selectDSGWSIntrinsic()
1726 .addReg(M0Base); in selectDSGWSIntrinsic()
1736 MIB.addReg(VSrc); in selectDSGWSIntrinsic()
1771 .addReg(PtrBase); in selectDSAppendConsume()
2005 .addReg(TmpReg, RegState::Kill, SubReg); in selectImageIntrinsic()
2014 MIB.addReg(VDataIn); // vdata input in selectImageIntrinsic()
2020 MIB.addReg(SrcOp.getReg()); in selectImageIntrinsic()
2024 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
2026 MIB.addReg(MI.getOperand(ArgOffset + Intr->SampIndex).getReg()); in selectImageIntrinsic()
2071 RegSeq.addReg(Zero).addImm(Sub); in selectImageIntrinsic()
2080 RegSeq.addReg(Undef).addImm(Sub); in selectImageIntrinsic()
2081 RegSeq.addReg(Zero).addImm(Parts.back()); in selectImageIntrinsic()
2083 MIB.addReg(Tied, RegState::Implicit); in selectImageIntrinsic()
2190 .addReg(CCReg); in selectG_SELECT()
2290 .addReg(SrcReg, 0, AMDGPU::sub0); in selectG_TRUNC()
2292 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_TRUNC()
2300 .addReg(HiReg) // $src0 in selectG_TRUNC()
2305 .addReg(LoReg, RegState::Implicit); in selectG_TRUNC()
2314 .addReg(HiReg); in selectG_TRUNC()
2317 .addReg(HiReg) in selectG_TRUNC()
2329 .addReg(LoReg) in selectG_TRUNC()
2330 .addReg(ImmReg); in selectG_TRUNC()
2332 .addReg(TmpReg0) in selectG_TRUNC()
2333 .addReg(TmpReg1); in selectG_TRUNC()
2426 .addReg(SrcReg) in selectG_SZA_EXT()
2428 .addReg(UndefReg) in selectG_SZA_EXT()
2445 .addReg(SrcReg); in selectG_SZA_EXT()
2453 .addReg(SrcReg) in selectG_SZA_EXT()
2470 .addReg(SrcReg); in selectG_SZA_EXT()
2482 .addReg(SrcReg, 0, SubReg) in selectG_SZA_EXT()
2490 .addReg(SrcReg, 0, SubReg) in selectG_SZA_EXT()
2492 .addReg(HiReg) in selectG_SZA_EXT()
2511 .addReg(SrcReg, 0, SubReg) in selectG_SZA_EXT()
2513 .addReg(UndefReg) in selectG_SZA_EXT()
2517 .addReg(ExtReg) in selectG_SZA_EXT()
2527 .addReg(SrcReg) in selectG_SZA_EXT()
2532 .addReg(SrcReg) in selectG_SZA_EXT()
2646 .addReg(LoReg) in selectG_CONSTANT()
2648 .addReg(HiReg) in selectG_CONSTANT()
2697 .addReg(Src, 0, AMDGPU::sub0); in selectG_FNEG()
2699 .addReg(Src, 0, AMDGPU::sub1); in selectG_FNEG()
2706 .addReg(HiReg) in selectG_FNEG()
2707 .addReg(ConstReg) in selectG_FNEG()
2710 .addReg(LoReg) in selectG_FNEG()
2712 .addReg(OpReg) in selectG_FNEG()
2739 .addReg(Src, 0, AMDGPU::sub0); in selectG_FABS()
2741 .addReg(Src, 0, AMDGPU::sub1); in selectG_FABS()
2748 .addReg(HiReg) in selectG_FABS()
2749 .addReg(ConstReg) in selectG_FABS()
2752 .addReg(LoReg) in selectG_FABS()
2754 .addReg(OpReg) in selectG_FABS()
2913 .addReg(CondReg) in selectG_BRCOND()
2914 .addReg(Exec) in selectG_BRCOND()
2928 .addReg(CondReg); in selectG_BRCOND()
2977 .addReg(SrcReg) in selectG_PTRMASK()
2978 .addReg(MaskReg) in selectG_PTRMASK()
3003 .addReg(SrcReg) in selectG_PTRMASK()
3004 .addReg(MaskReg); in selectG_PTRMASK()
3017 .addReg(SrcReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
3019 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
3032 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
3034 .addReg(LoReg) in selectG_PTRMASK()
3035 .addReg(MaskLo); in selectG_PTRMASK()
3046 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
3048 .addReg(HiReg) in selectG_PTRMASK()
3049 .addReg(MaskHi); in selectG_PTRMASK()
3053 .addReg(MaskedLo) in selectG_PTRMASK()
3055 .addReg(MaskedHi) in selectG_PTRMASK()
3130 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
3134 .addReg(SrcReg, 0, SubReg) in selectG_EXTRACT_VECTOR_ELT()
3135 .addReg(SrcReg, RegState::Implicit); in selectG_EXTRACT_VECTOR_ELT()
3145 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
3147 .addReg(SrcReg, 0, SubReg) in selectG_EXTRACT_VECTOR_ELT()
3148 .addReg(SrcReg, RegState::Implicit); in selectG_EXTRACT_VECTOR_ELT()
3156 .addReg(SrcReg) in selectG_EXTRACT_VECTOR_ELT()
3157 .addReg(IdxReg) in selectG_EXTRACT_VECTOR_ELT()
3214 .addReg(IdxReg); in selectG_INSERT_VECTOR_ELT()
3219 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
3220 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
3229 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
3230 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
3231 .addReg(IdxReg) in selectG_INSERT_VECTOR_ELT()
3290 .addReg(VIndex) in selectBufferLoadLds()
3292 .addReg(VOffset) in selectBufferLoadLds()
3295 MIB.addReg(IdxReg); in selectBufferLoadLds()
3297 MIB.addReg(VIndex); in selectBufferLoadLds()
3299 MIB.addReg(VOffset); in selectBufferLoadLds()
3405 .addReg(Addr); in selectGlobalLoadLds()
3408 MIB.addReg(VOffset); in selectGlobalLoadLds()
3510 .addReg(SrcReg); in selectWaveAddress()
3513 .addReg(SrcReg) in selectWaveAddress()
3542 .addReg(SrcReg) in selectStackRestore()
3548 .addReg(WaveAddr); in selectStackRestore()
3759 .addReg(Src); in copyToVGPRIfSrcFolded()
3784 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods0()
3802 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods0()
3827 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods()
3842 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3ModsNonCanonicalizing()
3857 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods()
3870 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3910 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3925 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PModsDOT()
3981 MIB.addReg(Elts[i]); in buildRegSequence()
4043 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF32NegAbs()
4069 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16Neg()
4100 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16NegAbs()
4145 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex8()
4167 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex16()
4180 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3OpSelMods()
4196 MIB.addReg( in selectVINTERPMods()
4214 MIB.addReg( in selectVINTERPModsHi()
4295 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdImm()
4315 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
4326 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgpr()
4327 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectSmrdSgpr()
4337 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgprImm()
4338 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSmrdSgprImm()
4373 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectFlatOffset()
4383 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectGlobalOffset()
4393 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectScratchOffset()
4439 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr in selectGlobalSAddr()
4441 MIB.addReg(HighBits); in selectGlobalSAddr()
4476 MIB.addReg(SAddr); in selectGlobalSAddr()
4479 MIB.addReg(VOffset); in selectGlobalSAddr()
4504 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()
4505 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
4555 .addReg(RHSDef->Reg) in selectScratchSAddr()
4564 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr in selectScratchSAddr()
4630 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4640 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4641 [=](MachineInstrBuilder &MIB) { MIB.addReg(LHS); }, // saddr in selectScratchSVAddr()
4666 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4669 MIB.addReg(HighBits); in selectMUBUFScratchOffen()
4708 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4714 MIB.addReg(VAddr); in selectMUBUFScratchOffen()
4874 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4877 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4899 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4902 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4914 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4959 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDS1Addr1Offset()
4981 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDSReadWrite2()
5064 .addReg(RSrc2) in buildRSRC()
5066 .addReg(RSrc3) in buildRSRC()
5079 .addReg(RSrcLo) in buildRSRC()
5081 .addReg(RSrcHi) in buildRSRC()
5253 MIB.addReg(RSrcReg); in selectMUBUFAddr64()
5256 MIB.addReg(VAddr); in selectMUBUFAddr64()
5260 MIB.addReg(SOffset); in selectMUBUFAddr64()
5262 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFAddr64()
5286 MIB.addReg(RSrcReg); in selectMUBUFOffset()
5290 MIB.addReg(SOffset); in selectMUBUFOffset()
5292 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFOffset()
5311 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectBUFSOffset()
5371 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSMRDBufferSgprImm()
5504 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixModsExt()
5517 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixMods()
5532 .addReg(I.getOperand(2).getReg()); in selectSBarrierSignalIsfirst()
5541 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); in selectSBarrierSignalIsfirst()
5598 .addReg(MemberCount); in selectNamedBarrierInst()
5610 .addReg(BarOp.getReg()) in selectNamedBarrierInst()
5611 .addReg(TmpReg0); in selectNamedBarrierInst()
5621 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::M0).addReg(M0Val); in selectNamedBarrierInst()
5645 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); in selectSBarrierLeave()