Home
last modified time | relevance | path

Searched refs:SrcVT (Results 1 – 25 of 49) sorted by relevance

12

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp840 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
841 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
1078 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && in SelectIToFP()
1079 SrcVT != MVT::i32 && SrcVT != MVT::i64) in SelectIToFP()
1116 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) { in SelectIToFP()
1120 SrcVT = MVT::i64; in SelectIToFP()
1188 MVT DstVT, SrcVT; in SelectFPToI() local
1206 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in SelectFPToI()
1811 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32) in PPCEmitIntExt()
1881 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16) in SelectTrunc()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1093 MVT DstVT, SrcVT; in selectFPToInt() local
1106 if (!isTypeLegal(SrcTy, SrcVT)) in selectFPToInt()
1109 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in selectFPToInt()
1204 MVT SrcVT = ArgVT; in processCallArgs() local
1212 MVT SrcVT = ArgVT; in processCallArgs() local
1776 EVT SrcVT, DestVT; in selectTrunc() local
1780 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in selectTrunc()
1826 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1844 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1870 switch (SrcVT.SimpleTy) { in emitIntZExt()
[all …]
H A DMipsMSAInstrInfo.td3606 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3608 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3609 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3666 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3674 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3679 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3683 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3687 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3689 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3693 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2831 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
2872 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
3950 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
4095 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
4096 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSL_ri()
4198 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
4199 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSR_ri()
4314 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitASR_ri()
4315 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitASR_ri()
4400 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && in emitIntExt()
[all …]
H A DAArch64ISelLowering.cpp4153 SrcVT = F32VT; in LowerVectorFP_TO_INT_SAT()
4213 } else if (SrcVT != MVT::f64 && SrcVT != MVT::f32 && SrcVT != MVT::f16) in LowerFP_TO_INT_SAT()
4218 if ((SrcVT == MVT::f64 || SrcVT == MVT::f32 || in LowerFP_TO_INT_SAT()
11125 assert((SrcVT.is64BitVector() || SrcVT.is128BitVector()) && in ReconstructShuffle()
19080 EVT SrcVT; in isExtendOrShiftOperand() local
19086 return SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8; in isExtendOrShiftOperand()
22866 (SrcVT.isFloatingPoint() && SrcVT.getSizeInBits() <= 16)) in performSelectCombine()
22873 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts); in performSelectCombine()
23083 if ((SrcVT != MVT::nxv4f32) && (SrcVT != MVT::nxv2f64) && in performScatterStoreCombine()
23086 ((SrcVT != MVT::nxv8f16) && (SrcVT != MVT::nxv8bf16)))) in performScatterStoreCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1231 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
1236 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1240 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandANY_EXTEND_VECTOR_INREG()
1242 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1258 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
1265 EVT SrcVT = Src.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1290 EVT SrcVT = Src.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
1295 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
1299 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandZERO_EXTEND_VECTOR_INREG()
1301 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
[all …]
H A DTargetLowering.cpp693 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
728 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyMultipleUseDemandedBits()
2398 unsigned InElts = SrcVT.isFixedLengthVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2444 unsigned InElts = SrcVT.isFixedLengthVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2508 unsigned InElts = SrcVT.isFixedLengthVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2661 SrcVT != MVT::f128) { in SimplifyDemandedBits()
2708 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2718 if (SrcVT.isVector()) { in SimplifyDemandedBits()
3102 if (!SrcVT.isVector()) in SimplifyDemandedVectorElts()
8219 if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) || in expandUINT_TO_FP()
[all …]
H A DLegalizeDAG.cpp735 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
748 (SrcVT != MVT::i1 || in LegalizeLoadOps()
916 EVT SVT = SrcVT.getScalarType(); in LegalizeLoadOps()
932 assert(!SrcVT.isVector() && in LegalizeLoadOps()
1766 EVT SrcVT = SrcOp.getValueType(); in EmitStackConvert() local
1771 if ((SrcVT.bitsGT(SlotVT) && in EmitStackConvert()
1791 if (SrcVT.bitsGT(SlotVT)) in EmitStackConvert()
2628 EVT SrcVT = Op0.getValueType(); in ExpandLegalINT_TO_FP() local
2704 if (((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) || in ExpandLegalINT_TO_FP()
2769 SrcVT.getSizeInBits() - 1 && in ExpandLegalINT_TO_FP()
[all …]
H A DFastISel.cpp1457 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1460 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1470 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1478 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1495 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1502 if (SrcVT == DstVT) { in selectBitCast()
1508 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1862 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1864 if (DstVT.bitsGT(SrcVT)) in selectOperator()
1866 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DLegalizeFloatTypes.cpp1031 static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted, in findFPToIntLibcall() argument
1040 LC = Signed ? RTLIB::getFPTOSINT(SrcVT, Promoted) in findFPToIntLibcall()
1041 : RTLIB::getFPTOUINT(SrcVT, Promoted); in findFPToIntLibcall()
1772 EVT SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP() local
1785 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1797 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1801 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1817 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1829 SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP()
1837 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandFloatRes_XINT_TO_FP()
[all …]
H A DDAGCombiner.cpp3722 if (DstVT == SrcVT) in getTruncatedUSUBSAT()
3735 DL, SrcVT); in getTruncatedUSUBSAT()
6790 if (!TLI.isTypeLegal(SrcVT)) in combineShiftAnd1ToBitTest()
7057 TLI.isTruncateFree(VT, SrcVT) && TLI.isZExtFree(SrcVT, VT) && in visitAND()
12890 EVT SrcVT = N0.getValueType(); in CombineExtLoad() local
12932 EVT SplitSrcVT = SrcVT; in CombineExtLoad()
23402 if (SrcVT.isVector()) { in visitBUILD_VECTOR()
23667 if (!SrcVT.isVector()) in combineConcatVectorOfCasts()
26100 SrcVT, SDLoc(N), SrcVec, DAG.getUNDEF(SrcVT), Mask, DAG); in visitSCALAR_TO_VECTOR()
26105 if (VT == SrcVT) in visitSCALAR_TO_VECTOR()
[all …]
H A DLegalizeVectorTypes.cpp586 EVT SrcVT = Src.getValueType(); in ScalarizeVecRes_FP_TO_XINT_SAT() local
2384 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_ExtendOp() local
2402 if (SrcVT.getVectorElementCount().isKnownEven() && in SplitVecRes_ExtendOp()
2829 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_FP_TO_XINT_SAT() local
4839 EVT SrcVT = Src.getValueType(); in WidenVecRes_FP_TO_XINT_SAT() local
4844 SrcVT = Src.getValueType(); in WidenVecRes_FP_TO_XINT_SAT()
4848 if (WidenNumElts != SrcVT.getVectorElementCount()) in WidenVecRes_FP_TO_XINT_SAT()
4860 EVT SrcVT = Src.getValueType(); in WidenVecRes_XRINT() local
4865 SrcVT = Src.getValueType(); in WidenVecRes_XRINT()
4869 if (WidenNumElts != SrcVT.getVectorElementCount()) in WidenVecRes_XRINT()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1342 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1358 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1359 SrcVT == MVT::i1) { in ARMEmitCmp()
1373 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1381 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1537 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1538 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
1545 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) { in SelectIToFP()
2588 EVT SrcVT, DestVT; in SelectTrunc() local
2592 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectTrunc()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1246 if (SrcVT != DstVT) { in X86SelectRet()
1247 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1255 if (SrcVT == MVT::i1) { in X86SelectRet()
1260 SrcVT = MVT::i8; in X86SelectRet()
1543 if (SrcVT == MVT::i1) { in X86SelectZExt()
1546 SrcVT = MVT::i8; in X86SelectZExt()
1601 if (SrcVT == MVT::i1) { in X86SelectSExt()
1612 SrcVT = MVT::i8; in X86SelectSExt()
2401 if (SrcVT != MVT::i32 && SrcVT != MVT::i64) in X86SelectIntToFP()
2527 if (SrcVT == MVT::i8) { in X86SelectTrunc()
[all …]
H A DX86ISelLowering.cpp9938 SrcVT = MVT::getVectorVT(SrcVT, NumSrcElts); in matchShuffleAsVTRUNC()
18983 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in lowerFPToIntToFP()
19184 if (SrcVT == MVT::v2i64 || SrcVT == MVT::v4i64) in LowerSINT_TO_FP()
19190 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && in LowerSINT_TO_FP()
20807 (SrcVT == MVT::v4f64 || SrcVT == MVT::v4f32 || SrcVT == MVT::v8f32) && in LowerFP_TO_INT()
20839 (SrcVT == MVT::v2f64 || SrcVT == MVT::v4f64 || SrcVT == MVT::v4f32) && in LowerFP_TO_INT()
21051 if (SrcVT != MVT::f32 && SrcVT != MVT::f64 && SrcVT != MVT::f80) { in LRINT_LLRINTHelper()
30827 assert((SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8 || in LowerBITCAST()
40067 if ((SrcVT == MVT::v2f64 || SrcVT == MVT::v4f32 || SrcVT == MVT::v2i64 || in combineTargetShuffle()
43001 (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) && in combineBitcast()
[all …]
H A DX86SelectionDAGInfo.cpp250 EVT SrcVT = Src.getValueType(); in emitConstantSizeRepmov() local
254 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.h1374 bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override;
1438 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1512 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td305 class isIntType<ValueType SrcVT> {
306 bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value));
1601 class isModifierType<ValueType SrcVT> {
1602 bit ret = !or(!eq(SrcVT.Value, f16.Value),
1603 !eq(SrcVT.Value, bf16.Value),
1604 !eq(SrcVT.Value, f32.Value),
1605 !eq(SrcVT.Value, f64.Value),
1606 !eq(SrcVT.Value, v2f16.Value),
1607 !eq(SrcVT.Value, v2i16.Value),
1609 !eq(SrcVT.Value, v2f32.Value),
[all …]
H A DAMDGPUISelLowering.cpp3307 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
3324 if (SrcVT != MVT::i64) in LowerUINT_TO_FP()
3353 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
3370 if (SrcVT != MVT::i64) in LowerSINT_TO_FP()
3402 assert(SrcVT == MVT::f32 || SrcVT == MVT::f64); in LowerFP_TO_INT64()
3428 if (SrcVT == MVT::f64) { in LowerFP_TO_INT64()
3431 SrcVT); in LowerFP_TO_INT64()
3434 SrcVT); in LowerFP_TO_INT64()
3587 if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) { in LowerFP_TO_INT()
3597 if (SrcVT == MVT::f16 || in LowerFP_TO_INT()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp932 EVT SrcVT = TLI->getValueType(DL, I->getType()); in run() local
933 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) in run()
936 if (TLI->getTypeAction(*Ctx, SrcVT) != TargetLowering::TypePromoteInteger) in run()
939 EVT PromotedVT = TLI->getTypeToTransformTo(*Ctx, SrcVT); in run()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1933 EVT SrcVT = Src.getValueType(); in LowerEXTEND_VECTOR_INREG() local
1935 if (SrcVT.getVectorElementType() == MVT::i1 || in LowerEXTEND_VECTOR_INREG()
1936 SrcVT.getVectorElementType() == MVT::i64) in LowerEXTEND_VECTOR_INREG()
2710 EVT SrcVT = In.getValueType(); in truncateVectorWithNARROW() local
2713 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2716 unsigned SrcSizeInBits = SrcVT.getSizeInBits(); in truncateVectorWithNARROW()
2717 unsigned NumElems = SrcVT.getVectorNumElements(); in truncateVectorWithNARROW()
2729 if (SrcVT.getScalarSizeInBits() > 16) { in truncateVectorWithNARROW()
2792 EVT SrcVT = Src.getValueType(); in performBitcastCombine() local
2797 SrcVT.isFixedLengthVector() && SrcVT.getScalarType() == MVT::i1) { in performBitcastCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h449 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
451 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
475 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DRISCVISelLowering.cpp1778 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || in isTruncateFree()
2792 MVT SrcContainerVT = SrcVT; in lowerFP_TO_INT_SAT()
7722 MVT ContainerVT = SrcVT; in lowerVectorTruncLike()
7752 if (SrcVT.isFixedLengthVector()) in lowerVectorTruncLike()
10637 SrcVT = getContainerForFixedLengthVector(SrcVT); in lowerVPFPIntConvOp()
10648 if (SrcVT.isInteger()) { in lowerVPFPIntConvOp()
10692 if (SrcVT.isInteger()) { in lowerVPFPIntConvOp()
12917 EVT SrcVT = Src.getValueType(); in narrowIndex() local
13873 MVT SrcContainerVT = SrcVT; in performFP_TO_INTCombine()
15958 if (SrcVT == VT) in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2736 static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) { in decideComp() argument
2737 if (SrcVT.isFloatingPoint()) { in decideComp()
2738 if (SrcVT == MVT::f128) in decideComp()
2745 static EVT decideCompType(EVT SrcVT) { in decideCompType() argument
2746 if (SrcVT == MVT::f128) in decideCompType()
2748 return SrcVT; in decideCompType()
2751 static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC, in safeWithoutCompWithNull() argument
2753 if (SrcVT.isFloatingPoint()) { in safeWithoutCompWithNull()
2758 return SrcVT != MVT::f128; in safeWithoutCompWithNull()
2773 return isSignedIntSetCC(CC) && SrcVT == MVT::i64; in safeWithoutCompWithNull()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h227 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;

12