198   bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
233   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
258   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
261   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
264   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1187   MVT SrcVT = RetVT;  in emitAddSub()  local
1213     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);  in emitAddSub()
1293     RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);  in emitAddSub()
2830   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectFPToInt()  local
2831   if (SrcVT == MVT::f128 || SrcVT == MVT::f16)  in selectFPToInt()
2835   if (SrcVT == MVT::f64) {  in selectFPToInt()
2869   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectIntToFP()  local
2872   if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {  in selectIntToFP()
2874         emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);  in selectIntToFP()
2880   if (SrcVT == MVT::i64) {  in selectIntToFP()
3040       MVT SrcVT = ArgVT;  in processCallArgs()  local
3041       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
3050       MVT SrcVT = ArgVT;  in processCallArgs()  local
3051       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3947   MVT SrcVT = SrcEVT.getSimpleVT();  in selectTrunc()  local
3950   if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&  in selectTrunc()
3951       SrcVT != MVT::i8)  in selectTrunc()
3967   if (SrcVT == MVT::i64) {  in selectTrunc()
4091 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSL_ri()  argument
4093   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSL_ri()
4095   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSL_ri()
4096           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSL_ri()
4104   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSL_ri()
4110     if (RetVT == SrcVT) {  in emitLSL_ri()
4117       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSL_ri()
4157   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSL_ri()
4194 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSR_ri()  argument
4196   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSR_ri()
4198   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSR_ri()
4199           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSR_ri()
4207   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4213     if (RetVT == SrcVT) {  in emitLSR_ri()
4220       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4258     Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4261     SrcVT = RetVT;  in emitLSR_ri()
4262     SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4273   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSR_ri()
4310 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitASR_ri()  argument
4312   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitASR_ri()
4314   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitASR_ri()
4315           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitASR_ri()
4323   unsigned SrcBits = SrcVT.getSizeInBits();  in emitASR_ri()
4329     if (RetVT == SrcVT) {  in emitASR_ri()
4336       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitASR_ri()
4378   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitASR_ri()
4390 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4400       ((SrcVT !=  MVT::i1) && (SrcVT !=  MVT::i8) &&  in emitIntExt()
4401        (SrcVT !=  MVT::i16) && (SrcVT !=  MVT::i32)))  in emitIntExt()
4407   switch (SrcVT.SimpleTy) {  in emitIntExt()
4500                                          MVT SrcVT) {  in optimizeIntExtLoad()  argument
4528   if (RetVT != MVT::i64 || SrcVT > MVT::i32) {  in optimizeIntExtLoad()
4557   MVT SrcVT;  in selectIntExt()  local
4561   if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))  in selectIntExt()
4565   if (optimizeIntExtLoad(I, RetVT, SrcVT))  in selectIntExt()
4576       if (RetVT == MVT::i64 && SrcVT != MVT::i64) {  in selectIntExt()
4591   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);  in selectIntExt()
4658       MVT SrcVT = VT;  in selectMul()  local
4664             SrcVT = VT;  in selectMul()
4673             SrcVT = VT;  in selectMul()
4685           emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);  in selectMul()
4721     MVT SrcVT = RetVT;  in selectShift()  local
4728           SrcVT = TmpVT;  in selectShift()
4737           SrcVT = TmpVT;  in selectShift()
4751       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4754       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4757       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4797   MVT RetVT, SrcVT;  in selectBitCast()  local
4799   if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))  in selectBitCast()
4805   if (RetVT == MVT::f32 && SrcVT == MVT::i32)  in selectBitCast()
4807   else if (RetVT == MVT::f64 && SrcVT == MVT::i64)  in selectBitCast()
4809   else if (RetVT == MVT::i32 && SrcVT == MVT::f32)  in selectBitCast()
4811   else if (RetVT == MVT::i64 && SrcVT == MVT::f64)  in selectBitCast()