978 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()  argument
985   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;  in isNarrowingProfitable()
1507   EVT SrcVT = Op.getOperand(0).getValueType();  in LowerEXTRACT_SUBVECTOR()  local
1511     unsigned NumSrcElt = SrcVT.getVectorNumElements();  in LowerEXTRACT_SUBVECTOR()
3305   EVT SrcVT = Src.getValueType();  in LowerUINT_TO_FP()  local
3307   if (SrcVT == MVT::i16) {  in LowerUINT_TO_FP()
3324   if (SrcVT != MVT::i64)  in LowerUINT_TO_FP()
3351   EVT SrcVT = Src.getValueType();  in LowerSINT_TO_FP()  local
3353   if (SrcVT == MVT::i16) {  in LowerSINT_TO_FP()
3370   if (SrcVT != MVT::i64)  in LowerSINT_TO_FP()
3400   EVT SrcVT = Src.getValueType();  in LowerFP_TO_INT64()  local
3402   assert(SrcVT == MVT::f32 || SrcVT == MVT::f64);  in LowerFP_TO_INT64()
3413   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src);  in LowerFP_TO_INT64()
3415   if (Signed && SrcVT == MVT::f32) {  in LowerFP_TO_INT64()
3424     Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc);  in LowerFP_TO_INT64()
3428   if (SrcVT == MVT::f64) {  in LowerFP_TO_INT64()
3431         SrcVT);  in LowerFP_TO_INT64()
3434         SrcVT);  in LowerFP_TO_INT64()
3437         llvm::bit_cast<float>(UINT32_C(/*2^-32*/ 0x2f800000)), SL, SrcVT);  in LowerFP_TO_INT64()
3439         llvm::bit_cast<float>(UINT32_C(/*-2^32*/ 0xcf800000)), SL, SrcVT);  in LowerFP_TO_INT64()
3442   SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0);  in LowerFP_TO_INT64()
3444   SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul);  in LowerFP_TO_INT64()
3446   SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc);  in LowerFP_TO_INT64()
3448   SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT  in LowerFP_TO_INT64()
3456   if (Signed && SrcVT == MVT::f32) {  in LowerFP_TO_INT64()
3573   EVT SrcVT = Src.getValueType();  in LowerFP_TO_INT()  local
3577   if (SrcVT == MVT::f16 && DestVT == MVT::i16)  in LowerFP_TO_INT()
3580   if (SrcVT == MVT::bf16) {  in LowerFP_TO_INT()
3587   if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {  in LowerFP_TO_INT()
3597   if (SrcVT == MVT::f16 ||  in LowerFP_TO_INT()
3598       (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) {  in LowerFP_TO_INT()
3607   if (SrcVT == MVT::f32 || SrcVT == MVT::f64)  in LowerFP_TO_INT()
3869     EVT SrcVT = Src.getValueType();  in performAssertSZExtCombine()  local
3870     if (SrcVT.bitsGE(ExtVT)) {  in performAssertSZExtCombine()
3871       SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);  in performAssertSZExtCombine()
4140     EVT SrcVT = Src.getValueType();  in performTruncateCombine()  local
4141     if (SrcVT.getScalarSizeInBits() > 32 &&  in performTruncateCombine()
4880     EVT SrcVT = Src.getValueType();  in performFNegCombine()  local
4883     SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,  in performFNegCombine()
4884                                   DAG.getConstant(0x8000, SL, SrcVT));  in performFNegCombine()
4966     EVT SrcVT = Src.getValueType();  in performFAbsCombine()  local
4969     SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,  in performFAbsCombine()
4970                                   DAG.getConstant(0x7fff, SL, SrcVT));  in performFAbsCombine()
5011         EVT SrcVT = Src.getValueType();  in PerformDAGCombine()  local
5014         if (SrcVT.getVectorNumElements() == NElts) {  in PerformDAGCombine()
5019           for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {  in PerformDAGCombine()