Home
last modified time | relevance | path

Searched refs:Register (Results 1 – 25 of 1164) sorted by relevance

12345678910>>...47

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h182 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) { in noteCloneVirtualRegister()
627 void replaceRegWith(Register FromReg, Register ToReg);
738 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
757 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
761 LLT getType(Register Reg) const { in getType()
794 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { in setRegAllocationHint()
803 void addRegAllocationHint(Register VReg, Register PrefReg) { in addRegAllocationHint()
810 void setSimpleHint(Register VReg, Register PrefReg) { in setSimpleHint()
823 std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const { in getRegAllocationHint()
832 Register getSimpleHint(Register VReg) const { in getSimpleHint()
[all …]
H A DVirtRegMap.h99 bool hasPhys(Register virtReg) const { in hasPhys()
105 MCRegister getPhys(Register virtReg) const { in getPhys()
116 bool hasShape(Register virtReg) const { in hasShape()
120 ShapeT getShape(Register virtReg) const { in getShape()
131 void clearVirt(Register virtReg) { in clearVirt()
153 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg()
161 Register getPreSplitReg(Register virtReg) const { in getPreSplitReg()
169 Register getOriginal(Register VirtReg) const { in getOriginal()
170 Register Orig = getPreSplitReg(VirtReg); in getOriginal()
187 int getStackSlot(Register virtReg) const { in getStackSlot()
[all …]
H A DFunctionLoweringInfo.h74 Register DemoteRegister;
82 DenseMap<const Value *, Register> ValueMap;
89 DenseMap<Register, const Value*> VirtReg2Value;
93 const Value *getValueFromVirtualReg(Register Vreg);
119 Register Reg;
147 DenseMap<Register, Register> RegFixups;
149 DenseSet<Register> RegsWithFixups;
214 Register CreateRegs(const Value *V);
218 Register InitializeRegForValue(const Value *V) { in InitializeRegForValue()
222 Register &R = ValueMap[V]; in InitializeRegForValue()
[all …]
H A DLiveRangeEdit.h56 virtual bool LRE_CanEraseVirtReg(Register) { return true; } in LRE_CanEraseVirtReg() argument
59 virtual void LRE_WillShrinkVirtReg(Register) {} in LRE_WillShrinkVirtReg() argument
63 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} in LRE_DidCloneVirtReg()
68 SmallVectorImpl<Register> &NewRegs;
107 void MRI_NoteNewVirtualRegister(Register VReg) override;
145 Register getReg() const { return getParent().reg(); } in getReg()
148 using iterator = SmallVectorImpl<Register>::const_iterator;
153 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } in get()
168 Register createFrom(Register OldReg);
176 Register create() { return createFrom(getReg()); } in create()
[all …]
H A DRegister.h19 class Register {
23 constexpr Register(unsigned Val = 0) : Reg(Val) {} in Reg()
24 constexpr Register(MCRegister Val) : Reg(Val) {} in Register() function
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index()
58 static Register index2StackSlot(int FI) { in index2StackSlot()
60 return Register(FI + MCRegister::FirstStackSlot); in index2StackSlot()
77 static unsigned virtReg2Index(Register Reg) { in virtReg2Index()
84 static Register index2VirtReg(unsigned Index) { in index2VirtReg()
150 template <> struct DenseMapInfo<Register> {
157 static unsigned getHashValue(const Register &Val) {
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h56 Register Addr;
57 Register Base;
58 Register Offset;
66 Register Base;
71 Register Reg;
495 std::tuple<Register, Register> &MatchInfo);
497 std::tuple<Register, Register> &MatchInfo);
545 std::pair<Register, Register> &MatchInfo);
644 bool tryReassocBinOp(unsigned Opc, Register DstReg, Register Op0,
881 computeRetValAgainstNaN(Register LHS, Register RHS,
[all …]
H A DUtils.h150 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
185 Register VReg;
191 getIConstantVRegValWithLookThrough(Register VReg,
198 Register VReg, const MachineRegisterInfo &MRI,
203 Register VReg;
209 getFConstantVRegValWithLookThrough(Register VReg,
226 Register Reg;
240 MachineInstr *getDefIgnoringCopies(Register Reg,
249 Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
381 Register Reg;
[all …]
H A DCallLowering.h118 Register SwiftErrorVReg;
143 Register DemoteRegister;
270 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
276 virtual void assignValueToAddress(Register ValVReg, Register Addr,
307 copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
314 Register extendRegister(Register ValReg, const CCValAssign &VA,
326 Register buildExtensionHint(const CCValAssign &VA, Register SrcReg,
330 void assignValueToReg(Register ValVReg, Register PhysReg,
454 ArrayRef<Register> VRegs, Register DemoteReg,
460 ArrayRef<Register> VRegs, Register DemoteReg) const;
[all …]
H A DGISelKnownBits.h36 SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
63 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
66 KnownBits getKnownBits(Register R);
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
72 APInt getKnownZeroes(Register R);
73 APInt getKnownOnes(Register R);
78 bool maskedValueIsZero(Register Val, const APInt &Mask) { in maskedValueIsZero()
84 bool signBitIsZero(Register Op);
[all …]
H A DLegalizationArtifactCombiner.h70 Register TruncSrc; in tryCombineAnyExt()
84 Register ExtSrc; in tryCombineAnyExt()
125 Register TruncSrc; in tryCombineZExt()
126 Register SextSrc; in tryCombineZExt()
160 Register ZextSrc; in tryCombineZExt()
215 Register ExtSrc; in tryCombineSExt()
547 static void replaceRegOrBuildCopy(Register DstReg, Register SrcReg, in replaceRegOrBuildCopy()
593 Register CurrentBest = Register();
805 Register findValueFromDefImpl(Register DefReg, unsigned StartBit, in findValueFromDefImpl()
862 Register findValueFromDef(Register DefReg, unsigned StartBit, in findValueFromDef()
[all …]
H A DLegalizerHelper.h131 Register coerceToScalar(Register Val);
199 void insertParts(Register DstReg, LLT ResultTy,
204 void mergeMixedSubvectors(Register DstReg, ArrayRef<Register> PartRegs);
206 void appendVectorElts(SmallVectorImpl<Register> &Elts, Register Reg);
219 Register SrcReg);
260 LegalizeResult lowerMemset(MachineInstr &MI, Register Dst, Register Val,
263 LegalizeResult lowerMemcpyInline(MachineInstr &MI, Register Dst, Register Src,
266 LegalizeResult lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
269 LegalizeResult lowerMemmove(MachineInstr &MI, Register Dst, Register Src,
297 Register getVectorElementPointer(Register VecPtr, LLT VecTy, Register Index);
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.h26 Register Reg;
28 Register UpdatedReg;
30 Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg) in Incoming()
34 Register createLaneMaskReg(MachineRegisterInfo *MRI, Register LaneMaskRegAttrs);
50 Register LaneMaskRegAttrs;
53 DenseSet<Register> PhiRegisters;
56 Register ExecReg;
66 bool isConstantLaneMask(Register Reg, bool &Val) const;
74 bool isLaneMaskReg(Register Reg) const { in isLaneMaskReg()
88 virtual void replaceDstReg(Register NewReg, Register OldReg,
[all …]
H A DAMDGPULegalizerInfo.h40 Register getSegmentAperture(unsigned AddrSpace,
86 std::pair<Register, Register>
91 bool legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
94 bool legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
105 ArrayRef<Register> Src0, ArrayRef<Register> Src1,
112 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
137 Register DstRemReg, Register Num,
138 Register Den) const;
141 Register DstRemReg, Register Num,
142 Register Den) const;
[all …]
H A DSIMachineFunctionInfo.h361 Register Reg;
398 Register LongBranchReservedReg;
484 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
531 Register SGPRForEXECCopy;
546 Register VGPRForAGPRCopy;
616 Register getScratchSGPRCopyDstReg(Register Reg) const {
740 Register addLDSKernelId();
754 Register addWorkGroupIDX() {
760 Register addWorkGroupIDY() {
766 Register addWorkGroupIDZ() {
[all …]
H A DAMDGPURegisterBankInfo.h48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
51 SmallSet<Register, 4> &SGPROperandRegs,
61 Register Src) const;
76 Register &VOffsetReg, Register &SOffsetReg,
91 Register Reg) const;
93 std::pair<Register, unsigned>
101 Register Ptr) const;
110 const ValueMapping *getSGPROpMapping(Register Reg,
115 const ValueMapping *getVGPROpMapping(Register Reg,
120 const ValueMapping *getAGPROpMapping(Register Reg,
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h48 Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap);
54 DenseMap<SDValue, Register> &VRBaseMap);
58 Register getVR(SDValue Op,
59 DenseMap<SDValue, Register> &VRBaseMap);
68 DenseMap<SDValue, Register> &VRBaseMap,
79 DenseMap<SDValue, Register> &VRBaseMap,
85 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
118 DenseMap<SDValue, Register> &VRBaseMap);
143 DenseMap<SDValue, Register> &VRBaseMap) { in EmitNode()
163 DenseMap<SDValue, Register> &VRBaseMap);
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h87 Register find(const Constant *C, MachineFunction *MF) { in find()
95 Register find(const Function *F, MachineFunction *MF) { in find()
106 SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
119 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
149 SPIRVType *getSPIRVTypeForVReg(Register VReg) const;
152 bool hasSPIRVTypeForVReg(Register VReg) const { in hasSPIRVTypeForVReg()
157 Register getSPIRVTypeID(const SPIRVType *SpirvType) const;
206 Register Reg);
228 Register getOrCreateIntCompositeOrNull(uint64_t Val,
253 Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param,
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp63 void MachineSSAUpdater::Initialize(Register V) { in Initialize()
89 return Register(); in LookForIdenticalPHI()
93 return Register(); in LookForIdenticalPHI()
112 return Register(); in LookForIdenticalPHI()
159 return Register(); in GetValueInMiddleOfBlock()
170 Register SingularValue; in GetValueInMiddleOfBlock()
182 SingularValue = Register(); in GetValueInMiddleOfBlock()
196 return Register(); in GetValueInMiddleOfBlock()
236 Register NewVR; in RewriteUse()
255 using ValT = Register;
[all …]
H A DRegAllocGreedy.h90 void setStage(Register Reg, LiveRangeStage Stage) { in setStage()
101 LiveRangeStage getOrInitStage(Register Reg) { in getOrInitStage()
108 void setCascade(Register Reg, unsigned Cascade) { in setCascade()
113 unsigned getOrAssignNewCascade(Register Reg) { in getOrAssignNewCascade()
132 Register Reg = *Begin; in setStage()
138 void LRE_DidCloneVirtReg(Register New, Register Old);
319 bool LRE_CanEraseVirtReg(Register) override;
320 void LRE_WillShrinkVirtReg(Register) override;
321 void LRE_DidCloneVirtReg(Register, Register) override;
396 Register Reg;
[all …]
H A DTwoAddressInstructionPass.cpp112 DenseMap<Register, Register> SrcRegMap;
117 DenseMap<Register, Register> DstRegMap;
121 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
138 bool regsAreCompatible(Register RegA, Register RegB) const;
141 DenseMap<Register, Register> &RegMap) const;
147 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
153 bool isProfitableToConv3Addr(Register RegA, Register RegB);
429 Register SrcReg; in findOnlyInterestingUse()
460 DenseMap<Register, Register>::iterator SI = RegMap.find(Reg); in getMappedReg()
550 const SmallVectorImpl<Register> &Set, Register Reg) const { in regOverlapsSet()
[all …]
H A DMachineRegisterInfo.cpp62 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
91 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
146 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister()
156 Register
170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister()
184 Register
201 Register Reg = Register::index2VirtReg(i); in clearVirtRegs()
258 verifyUseList(Register::index2VirtReg(i)); in verifyUseLists()
380 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) { in replaceRegWith()
462 return Register(); in getLiveInVirtReg()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h35 Register VarArgsFirstGPR;
36 Register VarArgsFirstFPR;
42 Register VRegADA;
64 void setSpillGPRRegs(Register Low, Register High, unsigned Offs) { in setSpillGPRRegs()
74 void setRestoreGPRRegs(Register Low, Register High, unsigned Offs) { in setRestoreGPRRegs()
82 Register getVarArgsFirstGPR() const { return VarArgsFirstGPR; } in getVarArgsFirstGPR()
83 void setVarArgsFirstGPR(Register GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
86 Register getVarArgsFirstFPR() const { return VarArgsFirstFPR; } in getVarArgsFirstFPR()
87 void setVarArgsFirstFPR(Register FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR()
108 Register getADAVirtualRegister() const { return VRegADA; } in getADAVirtualRegister()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp79 static Register buildLogBase2(Register V, MachineIRBuilder &MIB) { in buildLogBase2()
416 Register SrcReg; in applyShuffleToExtract()
1953 static Register peekThroughBitcast(Register Reg, in peekThroughBitcast()
3092 Register Src; in matchAshrShlToSextInreg()
3109 Register Src; in applyAshShlToSextInreg()
3126 Register R; in matchOverlappingAnd()
3393 Register X, Y; in applyXorOfAndWithSameReg()
4313 Register Src; in matchAndOrDisjointMask()
5574 Register Z; in matchCombineFAddFMAFMulToFMadOrFMA()
5643 auto buildMatchInfo = [=, &MI](Register U, Register V, Register Z, Register X, in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp38 void assignValueToReg(Register ValVReg, Register PhysReg,
40 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
43 Register getStackAddress(uint64_t Size, int64_t Offset,
51 void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
54 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
58 void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr, in assignValueToAddress()
77 Register SwiftErrorVReg) const { in lowerReturn()
145 void PPCIncomingValueHandler::assignValueToReg(Register ValVReg, in assignValueToReg()
146 Register PhysReg, in assignValueToReg()
153 Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, in assignValueToAddress()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp69 const Register ReservedRegs[] = { in getReservedRegs()
136 Register clobber;
243 Register SrcReg = MI.getOperand(3).getReg(); in processSTQ()
264 Register DestReg = MI.getOperand(0).getReg(); in processLDQ()
296 Register SrcReg = MI.getOperand(3).getReg(); in processSTVM()
300 Register TmpReg = VE::SX16; in processSTVM()
334 Register DestReg = MI.getOperand(0).getReg(); in processLDVM()
374 Register SrcReg = MI.getOperand(3).getReg(); in processSTVM512()
380 Register TmpReg = VE::SX16; in processSTVM512()
425 Register TmpReg = VE::SX16; in processLDVM512()
[all …]

12345678910>>...47