Lines Matching refs:Register

361     Register Reg;
366   PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
368   Register getReg() const { return Reg; }
384   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
388   Register FrameOffsetReg = AMDGPU::FP_REG;
393   Register StackPtrOffsetReg = AMDGPU::SP_REG;
398   Register LongBranchReservedReg;
483   void MRI_NoteNewVirtualRegister(Register Reg) override;
484   void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
504   SmallVector<Register, 2> SpillVGPRs;
505   SmallVector<Register, 2> SpillPhysVGPRs;
506   using WWMSpillsMap = MapVector<Register, int>;
515   using ReservedRegSet = SmallSetVector<Register, 8>;
523       DenseMap<Register, PrologEpilogSGPRSaveRestoreInfo>;
531   Register SGPRForEXECCopy;
546   Register VGPRForAGPRCopy;
555   Register getVGPRForAGPRCopy() const {
559   void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
579   void reserveWWMRegister(Register Reg) { WWMReservedRegs.insert(Reg); }
591   ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
604   void addToPrologEpilogSGPRSpills(Register Reg,
611   bool hasPrologEpilogSGPRSpillEntry(Register Reg) const {
616   Register getScratchSGPRCopyDstReg(Register Reg) const {
626   void getAllScratchSGPRCopyDstRegs(SmallVectorImpl<Register> &Regs) const {
636                    [FI](const std::pair<Register,
645   getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const {
660   void setFlag(Register Reg, uint8_t Flag) {
666   bool checkFlag(Register Reg, uint8_t Flag) const {
675   void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size = 4,
680       SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
681       SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const;
687   Register getSGPRForEXECCopy() const { return SGPRForEXECCopy; }
689   void setSGPRForEXECCopy(Register Reg) { SGPRForEXECCopy = Reg; }
733   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
734   Register addDispatchPtr(const SIRegisterInfo &TRI);
735   Register addQueuePtr(const SIRegisterInfo &TRI);
736   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
737   Register addDispatchID(const SIRegisterInfo &TRI);
738   Register addFlatScratchInit(const SIRegisterInfo &TRI);
739   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
740   Register addLDSKernelId();
747   Register addReservedUserSGPR() {
748     Register Next = getNextUserSGPR();
754   Register addWorkGroupIDX() {
760   Register addWorkGroupIDY() {
766   Register addWorkGroupIDZ() {
772   Register addWorkGroupInfo() {
793   Register addPrivateSegmentWaveByteOffset() {
800   void setPrivateSegmentWaveByteOffset(Register Reg) {
862   Register getGITPtrLoReg(const MachineFunction &MF) const;
880   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
886   Register getScratchRSrcReg() const {
890   void setScratchRSrcReg(Register Reg) {
895   Register getFrameOffsetReg() const {
899   void setFrameOffsetReg(Register Reg) {
904   void setStackPtrOffsetReg(Register Reg) {
909   void setLongBranchReservedReg(Register Reg) { LongBranchReservedReg = Reg; }
915   Register getStackPtrOffsetReg() const {
919   Register getLongBranchReservedReg() const { return LongBranchReservedReg; }
921   Register getQueuePtrUserSGPR() const {
925   Register getImplicitBufferPtrUserSGPR() const {