Lines Matching refs:Register
79 static Register buildLogBase2(Register V, MachineIRBuilder &MIB) { in buildLogBase2()
161 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith()
162 Register ToReg) const { in replaceRegWith()
175 Register ToReg) const { in replaceRegOpWith()
193 const RegisterBank *CombinerHelper::getRegBank(Register Reg) const { in getRegBank()
197 void CombinerHelper::setRegBank(Register Reg, const RegisterBank *RegBank) { in setRegBank()
212 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
213 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
217 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
218 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
225 SmallVector<Register, 4> Ops; in tryCombineConcatVectors()
234 SmallVectorImpl<Register> &Ops) { in matchCombineConcatVectors()
244 Register Reg = MO.getReg(); in matchCombineConcatVectors()
279 MachineInstr &MI, bool IsUndef, const ArrayRef<Register> Ops) { in applyCombineConcatVectors()
282 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
284 Register NewDstReg = MRI.cloneVirtualRegister(DstReg); in applyCombineConcatVectors()
301 SmallVector<Register, 4> Ops; in tryCombineShuffleVector()
310 SmallVectorImpl<Register> &Ops) { in matchCombineShuffleVector()
314 Register Src1 = MI.getOperand(1).getReg(); in matchCombineShuffleVector()
368 Register UndefReg; in matchCombineShuffleVector()
369 Register Src2 = MI.getOperand(2).getReg(); in matchCombineShuffleVector()
386 const ArrayRef<Register> Ops) { in applyCombineShuffleVector()
387 Register DstReg = MI.getOperand(0).getReg(); in applyCombineShuffleVector()
389 Register NewDstReg = MRI.cloneVirtualRegister(DstReg); in applyCombineShuffleVector()
409 Register DstReg = MI.getOperand(0).getReg(); in applyShuffleToExtract()
413 Register Src1 = MI.getOperand(1).getReg(); in applyShuffleToExtract()
416 Register SrcReg; in applyShuffleToExtract()
560 Register LoadReg = LoadMI->getDstReg(); in matchCombineExtendingLoads()
627 Register ChosenDstReg = Preferred.MI->getOperand(0).getReg(); in applyCombineExtendingLoads()
644 Register NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg()); in applyCombineExtendingLoads()
667 Register UseDstReg = UseMI->getOperand(0).getReg(); in applyCombineExtendingLoads()
742 Register Dst = MI.getOperand(0).getReg(); in matchCombineLoadWithAndMask()
756 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineLoadWithAndMask()
763 Register LoadReg = LoadMI->getDstReg(); in matchCombineLoadWithAndMask()
765 Register PtrReg = LoadMI->getPointerReg(); in matchCombineLoadWithAndMask()
841 Register SrcReg = MI.getOperand(1).getReg(); in matchSextTruncSextLoad()
842 Register LoadUser = SrcReg; in matchSextTruncSextLoad()
847 Register TruncSrc; in matchSextTruncSextLoad()
873 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in matchSextInRegOfLoad() argument
876 Register DstReg = MI.getOperand(0).getReg(); in matchSextInRegOfLoad()
883 Register SrcReg = MI.getOperand(1).getReg(); in matchSextInRegOfLoad()
925 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in applySextInRegOfLoad() argument
927 Register LoadReg; in applySextInRegOfLoad()
1016 bool CombinerHelper::findPostIndexCandidate(GLoadStore &LdSt, Register &Addr, in findPostIndexCandidate()
1017 Register &Base, Register &Offset, in findPostIndexCandidate()
1026 Register Ptr = LdSt.getPointerReg(); in findPostIndexCandidate()
1088 Register PtrAddDefReg = BasePtrUseDef->getReg(0); in findPostIndexCandidate()
1112 bool CombinerHelper::findPreIndexCandidate(GLoadStore &LdSt, Register &Addr, in findPreIndexCandidate()
1113 Register &Base, Register &Offset) { in findPreIndexCandidate()
1177 Register Vector = MI.getOperand(1).getReg(); in matchCombineExtractedVectorLoad()
1221 Register VecPtr = LoadMI->getPointerReg(); in matchCombineExtractedVectorLoad()
1243 Register Result = MI.getOperand(0).getReg(); in matchCombineExtractedVectorLoad()
1244 Register Index = MI.getOperand(2).getReg(); in matchCombineExtractedVectorLoad()
1250 Register finalPtr = Helper.getVectorElementPointer( in matchCombineExtractedVectorLoad()
1337 Register Src1 = MI.getOperand(1).getReg(); in matchCombineDivRem()
1383 Register DestDivReg, DestRemReg; in applyCombineDivRem()
1557 Register Add2 = MI.getOperand(1).getReg(); in matchPtrAddImmedChain()
1558 Register Imm1 = MI.getOperand(2).getReg(); in matchPtrAddImmedChain()
1567 Register Base = Add2Def->getOperand(1).getReg(); in matchPtrAddImmedChain()
1568 Register Imm2 = Add2Def->getOperand(2).getReg(); in matchPtrAddImmedChain()
1636 Register Shl2 = MI.getOperand(1).getReg(); in matchShiftImmedChain()
1637 Register Imm1 = MI.getOperand(2).getReg(); in matchShiftImmedChain()
1646 Register Base = Shl2Def->getOperand(1).getReg(); in matchShiftImmedChain()
1647 Register Imm2 = Shl2Def->getOperand(2).getReg(); in matchShiftImmedChain()
1692 Register NewImm = Builder.buildConstant(ImmTy, Imm).getReg(0); in applyShiftImmedChain()
1720 Register LogicDest = MI.getOperand(1).getReg(); in matchShiftOfShiftedLogic()
1731 const Register C1 = MI.getOperand(2).getReg(); in matchShiftOfShiftedLogic()
1755 Register LogicMIReg1 = LogicMI->getOperand(1).getReg(); in matchShiftOfShiftedLogic()
1757 Register LogicMIReg2 = LogicMI->getOperand(2).getReg(); in matchShiftOfShiftedLogic()
1792 Register Const = Builder.buildConstant(ShlType, MatchInfo.ValSum).getReg(0); in applyShiftOfShiftedLogic()
1794 Register Shift1Base = MatchInfo.Shift2->getOperand(1).getReg(); in applyShiftOfShiftedLogic()
1795 Register Shift1 = in applyShiftOfShiftedLogic()
1805 Register Shift2Const = MI.getOperand(2).getReg(); in applyShiftOfShiftedLogic()
1806 Register Shift2 = Builder in applyShiftOfShiftedLogic()
1811 Register Dest = MI.getOperand(0).getReg(); in applyShiftOfShiftedLogic()
1825 Register DstReg = Shl.getReg(0); in matchCommuteShift()
1826 Register SrcReg = Shl.getReg(1); in matchCommuteShift()
1827 Register ShiftReg = Shl.getReg(2); in matchCommuteShift()
1828 Register X, C1; in matchCommuteShift()
1886 Register LHS = MI.getOperand(1).getReg(); in matchCombineShlOfExtend()
1888 Register ExtSrc; in matchCombineShlOfExtend()
1894 Register RHS = MI.getOperand(2).getReg(); in matchCombineShlOfExtend()
1922 Register ExtSrcReg = MatchData.Reg; in applyCombineShlOfExtend()
1935 Register &MatchInfo) { in matchCombineMergeUnmerge()
1937 SmallVector<Register, 16> MergedValues; in matchCombineMergeUnmerge()
1953 static Register peekThroughBitcast(Register Reg, in peekThroughBitcast()
1962 MachineInstr &MI, SmallVectorImpl<Register> &Operands) { in matchCombineUnmergeMergeToPlainValues()
1966 Register SrcReg = peekThroughBitcast(Unmerge.getSourceReg(), MRI); in matchCombineUnmergeMergeToPlainValues()
1986 MachineInstr &MI, SmallVectorImpl<Register> &Operands) { in applyCombineUnmergeMergeToPlainValues()
1998 Register DstReg = MI.getOperand(Idx).getReg(); in applyCombineUnmergeMergeToPlainValues()
1999 Register SrcReg = Operands[Idx]; in applyCombineUnmergeMergeToPlainValues()
2020 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in matchCombineUnmergeConstant()
2051 Register DstReg = MI.getOperand(Idx).getReg(); in applyCombineUnmergeConstant()
2061 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in matchCombineUnmergeUndef()
2065 Register DstReg = MI.getOperand(Idx).getReg(); in matchCombineUnmergeUndef()
2085 Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg(); in applyCombineUnmergeWithDeadLanesToTrunc()
2094 Register Dst0Reg = MI.getOperand(0).getReg(); in applyCombineUnmergeWithDeadLanesToTrunc()
2107 Register Dst0Reg = MI.getOperand(0).getReg(); in matchCombineUnmergeZExtToZExt()
2114 Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg(); in matchCombineUnmergeZExtToZExt()
2119 Register ZExtSrcReg; in matchCombineUnmergeZExtToZExt()
2134 Register Dst0Reg = MI.getOperand(0).getReg(); in applyCombineUnmergeZExtToZExt()
2141 Register ZExtSrcReg = ZExtInstr->getOperand(1).getReg(); in applyCombineUnmergeZExtToZExt()
2155 Register ZeroReg; in applyCombineUnmergeZExtToZExt()
2191 Register DstReg = MI.getOperand(0).getReg(); in applyCombineShiftToUnmerge()
2192 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineShiftToUnmerge()
2205 Register Narrowed = Unmerge.getReg(1); in applyCombineShiftToUnmerge()
2220 Register Narrowed = Unmerge.getReg(0); in applyCombineShiftToUnmerge()
2273 bool CombinerHelper::matchCombineI2PToP2I(MachineInstr &MI, Register &Reg) { in matchCombineI2PToP2I()
2275 Register DstReg = MI.getOperand(0).getReg(); in matchCombineI2PToP2I()
2277 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineI2PToP2I()
2282 void CombinerHelper::applyCombineI2PToP2I(MachineInstr &MI, Register &Reg) { in applyCombineI2PToP2I()
2284 Register DstReg = MI.getOperand(0).getReg(); in applyCombineI2PToP2I()
2290 void CombinerHelper::applyCombineP2IToI2P(MachineInstr &MI, Register &Reg) { in applyCombineP2IToI2P()
2292 Register DstReg = MI.getOperand(0).getReg(); in applyCombineP2IToI2P()
2299 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2301 Register LHS = MI.getOperand(1).getReg(); in matchCombineAddP2IToPtrAdd()
2302 Register RHS = MI.getOperand(2).getReg(); in matchCombineAddP2IToPtrAdd()
2308 for (Register SrcReg : {LHS, RHS}) { in matchCombineAddP2IToPtrAdd()
2324 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2325 Register Dst = MI.getOperand(0).getReg(); in applyCombineAddP2IToPtrAdd()
2326 Register LHS = MI.getOperand(1).getReg(); in applyCombineAddP2IToPtrAdd()
2327 Register RHS = MI.getOperand(2).getReg(); in applyCombineAddP2IToPtrAdd()
2345 Register LHS = PtrAdd.getBaseReg(); in matchCombineConstPtrAddToI2P()
2346 Register RHS = PtrAdd.getOffsetReg(); in matchCombineConstPtrAddToI2P()
2366 Register Dst = PtrAdd.getReg(0); in applyCombineConstPtrAddToI2P()
2373 bool CombinerHelper::matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) { in matchCombineAnyExtTrunc()
2375 Register DstReg = MI.getOperand(0).getReg(); in matchCombineAnyExtTrunc()
2376 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineAnyExtTrunc()
2377 Register OriginalSrcReg = getSrcRegIgnoringCopies(SrcReg, MRI); in matchCombineAnyExtTrunc()
2385 bool CombinerHelper::matchCombineZextTrunc(MachineInstr &MI, Register &Reg) { in matchCombineZextTrunc()
2387 Register DstReg = MI.getOperand(0).getReg(); in matchCombineZextTrunc()
2388 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineZextTrunc()
2400 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in matchCombineExtOfExt() argument
2405 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineExtOfExt()
2406 Register OriginalSrcReg = getSrcRegIgnoringCopies(SrcReg, MRI); in matchCombineExtOfExt()
2424 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in applyCombineExtOfExt() argument
2430 Register Reg = std::get<0>(MatchInfo); in applyCombineExtOfExt()
2447 Register DstReg = MI.getOperand(0).getReg(); in applyCombineExtOfExt()
2455 MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) { in matchCombineTruncOfExt() argument
2457 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineTruncOfExt()
2469 MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) { in applyCombineTruncOfExt() argument
2471 Register SrcReg = MatchInfo.first; in applyCombineTruncOfExt()
2473 Register DstReg = MI.getOperand(0).getReg(); in applyCombineTruncOfExt()
2509 Register DstReg = MI.getOperand(0).getReg(); in matchCombineTruncOfShift()
2510 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineTruncOfShift()
2574 Register Dst = MI.getOperand(0).getReg(); in applyCombineTruncOfShift()
2577 Register ShiftAmt = ShiftMI->getOperand(2).getReg(); in applyCombineTruncOfShift()
2578 Register ShiftSrc = ShiftMI->getOperand(1).getReg(); in applyCombineTruncOfShift()
2581 Register NewShift = in applyCombineTruncOfShift()
2770 Register OldReg = MI.getOperand(0).getReg(); in replaceSingleDefInstWithOperand()
2771 Register Replacement = MI.getOperand(OpIdx).getReg(); in replaceSingleDefInstWithOperand()
2778 Register Replacement) { in replaceSingleDefInstWithReg()
2780 Register OldReg = MI.getOperand(0).getReg(); in replaceSingleDefInstWithReg()
2788 Register ConstReg = MI.getOperand(ConstIdx).getReg(); in matchConstantLargerBitWidth()
2805 Register ConstReg = MI.getOperand(3).getReg(); in applyFunnelShiftConstantModulo()
2893 MachineInstr &MI, std::tuple<Register, Register> &MatchInfo) { in matchSimplifyAddToSub() argument
2894 Register LHS = MI.getOperand(1).getReg(); in matchSimplifyAddToSub()
2895 Register RHS = MI.getOperand(2).getReg(); in matchSimplifyAddToSub()
2896 Register &NewLHS = std::get<0>(MatchInfo); in matchSimplifyAddToSub()
2897 Register &NewRHS = std::get<1>(MatchInfo); in matchSimplifyAddToSub()
2902 auto CheckFold = [&](Register &MaybeSub, Register &MaybeNewLHS) { in matchSimplifyAddToSub()
2913 MachineInstr &MI, SmallVectorImpl<Register> &MatchInfo) { in matchCombineInsertVecElts()
2916 Register DstReg = MI.getOperand(0).getReg(); in matchCombineInsertVecElts()
2928 Register TmpReg; in matchCombineInsertVecElts()
2954 MachineInstr &MI, SmallVectorImpl<Register> &MatchInfo) { in applyCombineInsertVecElts()
2956 Register UndefReg; in applyCombineInsertVecElts()
2973 MachineInstr &MI, std::tuple<Register, Register> &MatchInfo) { in applySimplifyAddToSub() argument
2975 Register SubLHS, SubRHS; in applySimplifyAddToSub()
2994 Register Dst = MI.getOperand(0).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
2995 Register LHSReg = MI.getOperand(1).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
2996 Register RHSReg = MI.getOperand(2).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
3016 Register X = LeftHandInst->getOperand(1).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
3017 Register Y = RightHandInst->getOperand(1).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
3024 Register ExtraHandOpSrcReg; in matchHoistLogicOpWithSameOpcodeHands()
3089 MachineInstr &MI, std::tuple<Register, int64_t> &MatchInfo) { in matchAshrShlToSextInreg() argument
3092 Register Src; in matchAshrShlToSextInreg()
3107 MachineInstr &MI, std::tuple<Register, int64_t> &MatchInfo) { in applyAshShlToSextInreg() argument
3109 Register Src; in applyAshShlToSextInreg()
3123 Register Dst = MI.getOperand(0).getReg(); in matchOverlappingAnd()
3126 Register R; in matchOverlappingAnd()
3146 Register &Replacement) { in matchRedundantAnd()
3166 Register AndDst = MI.getOperand(0).getReg(); in matchRedundantAnd()
3167 Register LHS = MI.getOperand(1).getReg(); in matchRedundantAnd()
3168 Register RHS = MI.getOperand(2).getReg(); in matchRedundantAnd()
3194 bool CombinerHelper::matchRedundantOr(MachineInstr &MI, Register &Replacement) { in matchRedundantOr()
3206 Register OrDst = MI.getOperand(0).getReg(); in matchRedundantOr()
3207 Register LHS = MI.getOperand(1).getReg(); in matchRedundantOr()
3208 Register RHS = MI.getOperand(2).getReg(); in matchRedundantOr()
3236 Register Src = MI.getOperand(1).getReg(); in matchRedundantSExtInReg()
3250 SmallVectorImpl<Register> &RegsToNegate) { in matchNotCmp()
3254 Register XorSrc; in matchNotCmp()
3255 Register CstReg; in matchNotCmp()
3272 Register Reg = RegsToNegate[I]; in matchNotCmp()
3327 SmallVectorImpl<Register> &RegsToNegate) { in applyNotCmp()
3328 for (Register Reg : RegsToNegate) { in applyNotCmp()
3359 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in matchXorOfAndWithSameReg() argument
3362 Register &X = MatchInfo.first; in matchXorOfAndWithSameReg()
3363 Register &Y = MatchInfo.second; in matchXorOfAndWithSameReg()
3364 Register AndReg = MI.getOperand(1).getReg(); in matchXorOfAndWithSameReg()
3365 Register SharedReg = MI.getOperand(2).getReg(); in matchXorOfAndWithSameReg()
3390 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in applyXorOfAndWithSameReg() argument
3393 Register X, Y; in applyXorOfAndWithSameReg()
3405 Register DstReg = PtrAdd.getReg(0); in matchPtrAddZero()
3431 Register DstReg = MI.getOperand(0).getReg(); in applySimplifyURemByPow2()
3432 Register Src0 = MI.getOperand(1).getReg(); in applySimplifyURemByPow2()
3433 Register Pow2Src1 = MI.getOperand(2).getReg(); in applySimplifyURemByPow2()
3446 Register LHS = MI.getOperand(1).getReg(); in matchFoldBinOpIntoSelect()
3447 Register RHS = MI.getOperand(2).getReg(); in matchFoldBinOpIntoSelect()
3449 Register OtherOperandReg = RHS; in matchFoldBinOpIntoSelect()
3502 Register Dst = MI.getOperand(0).getReg(); in applyFoldBinOpIntoSelect()
3503 Register LHS = MI.getOperand(1).getReg(); in applyFoldBinOpIntoSelect()
3504 Register RHS = MI.getOperand(2).getReg(); in applyFoldBinOpIntoSelect()
3507 Register SelectCond = Select->getOperand(1).getReg(); in applyFoldBinOpIntoSelect()
3508 Register SelectTrue = Select->getOperand(2).getReg(); in applyFoldBinOpIntoSelect()
3509 Register SelectFalse = Select->getOperand(3).getReg(); in applyFoldBinOpIntoSelect()
3514 Register FoldTrue, FoldFalse; in applyFoldBinOpIntoSelect()
3536 std::optional<SmallVector<Register, 8>>
3562 SmallVector<Register, 8> RegsToVisit; in findCandidatesForLoadOrCombine()
3573 Register OrLHS = Curr->getOperand(1).getReg(); in findCandidatesForLoadOrCombine()
3574 Register OrRHS = Curr->getOperand(2).getReg(); in findCandidatesForLoadOrCombine()
3608 matchLoadAndBytePosition(Register Reg, unsigned MemSizeInBits, in matchLoadAndBytePosition()
3612 Register MaybeLoad; in matchLoadAndBytePosition()
3637 const SmallVector<Register, 8> &RegsToVisit, const unsigned MemSizeInBits) { in findLoadOffsetsForLoadOrCombine() argument
3663 Register BasePtr; in findLoadOffsetsForLoadOrCombine()
3695 Register LoadPtr; in findLoadOffsetsForLoadOrCombine()
3782 Register Dst = MI.getOperand(0).getReg(); in matchLoadOrCombine()
3853 Register Ptr = LowestIdxLoad->getPointerReg(); in matchLoadOrCombine()
3873 Register LoadDst = NeedsBSwap ? MRI.cloneVirtualRegister(Dst) : Dst; in matchLoadOrCombine()
3884 Register DstReg = PHI.getReg(0); in matchExtendThroughPhis()
3938 Register DstReg = ExtMI->getOperand(0).getReg(); in applyExtendThroughPhis()
3981 Register &Reg) { in matchExtractVecEltBuildVec()
3985 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec()
4015 Register &Reg) { in applyExtractVecEltBuildVec()
4019 Register DstReg = MI.getOperand(0).getReg(); in applyExtractVecEltBuildVec()
4034 SmallVectorImpl<std::pair<Register, MachineInstr *>> &SrcDstPairs) { in matchExtractAllEltsFromBuildVector() argument
4052 Register DstReg = MI.getOperand(0).getReg(); in matchExtractAllEltsFromBuildVector()
4076 SmallVectorImpl<std::pair<Register, MachineInstr *>> &SrcDstPairs) { in applyExtractAllEltsFromBuildVector() argument
4103 Register Dst = MI.getOperand(0).getReg(); in matchOrShiftToFunnelShift()
4107 Register ShlSrc, ShlAmt, LShrSrc, LShrAmt, Amt; in matchOrShiftToFunnelShift()
4156 Register X = MI.getOperand(1).getReg(); in matchFunnelShiftToRotate()
4157 Register Y = MI.getOperand(2).getReg(); in matchFunnelShiftToRotate()
4182 Register AmtReg = MI.getOperand(2).getReg(); in matchRotateOutOfRange()
4198 Register Amt = MI.getOperand(2).getReg(); in applyRotateOutOfRange()
4277 Register Dst = MI.getOperand(0).getReg(); in matchICmpToLHSKnownBits()
4285 Register LHS = MI.getOperand(2).getReg(); in matchICmpToLHSKnownBits()
4313 Register Src; in matchAndOrDisjointMask()
4314 Register AndMaskReg; in matchAndOrDisjointMask()
4341 Register Dst = MI.getOperand(0).getReg(); in matchBitfieldExtractFromSExtInReg()
4342 Register Src = MI.getOperand(1).getReg(); in matchBitfieldExtractFromSExtInReg()
4348 Register ShiftSrc; in matchBitfieldExtractFromSExtInReg()
4370 Register Dst = MI.getOperand(0).getReg(); in matchBitfieldExtractFromAnd()
4377 Register ShiftSrc; in matchBitfieldExtractFromAnd()
4407 const Register Dst = MI.getOperand(0).getReg(); in matchBitfieldExtractFromShr()
4419 Register ShlSrc; in matchBitfieldExtractFromShr()
4456 const Register Dst = MI.getOperand(0).getReg(); in matchBitfieldExtractFromShrAnd()
4463 Register AndSrc; in matchBitfieldExtractFromShrAnd()
4512 Register Src1Reg = PtrAdd.getBaseReg(); in reassociationCanBreakAddressingModePattern()
4517 Register Src2Reg = PtrAdd.getOffsetReg(); in reassociationCanBreakAddressingModePattern()
4540 Register DefReg = ConvUseMI->getOperand(0).getReg(); in reassociationCanBreakAddressingModePattern()
4577 Register Src1Reg = MI.getOperand(1).getReg(); in matchReassocConstantInnerRHS()
4603 Register LHSBase; in matchReassocConstantInnerLHS()
4615 Register RHSReg = MI.getOffsetReg(); in matchReassocConstantInnerLHS()
4637 Register Src2Reg = MI.getOperand(2).getReg(); in matchReassocFoldConstantsInSubTree()
4638 Register LHSSrc1 = LHSPtrAdd->getBaseReg(); in matchReassocFoldConstantsInSubTree()
4639 Register LHSSrc2 = LHSPtrAdd->getOffsetReg(); in matchReassocFoldConstantsInSubTree()
4689 bool CombinerHelper::tryReassocBinOp(unsigned Opc, Register DstReg, in tryReassocBinOp()
4690 Register OpLHS, Register OpRHS, in tryReassocBinOp()
4699 Register OpLHSLHS = OpLHSDef->getOperand(1).getReg(); in tryReassocBinOp()
4700 Register OpLHSRHS = OpLHSDef->getOperand(2).getReg(); in tryReassocBinOp()
4735 Register DstReg = MI.getOperand(0).getReg(); in matchReassocCommBinOp()
4736 Register LHSReg = MI.getOperand(1).getReg(); in matchReassocCommBinOp()
4737 Register RHSReg = MI.getOperand(2).getReg(); in matchReassocCommBinOp()
4748 Register SrcOp = MI.getOperand(1).getReg(); in matchConstantFoldCastOp()
4759 Register Op1 = MI.getOperand(1).getReg(); in matchConstantFoldBinOp()
4760 Register Op2 = MI.getOperand(2).getReg(); in matchConstantFoldBinOp()
4769 Register Op1 = MI.getOperand(1).getReg(); in matchConstantFoldFPBinOp()
4770 Register Op2 = MI.getOperand(2).getReg(); in matchConstantFoldFPBinOp()
4823 Register Dst = MI.getOperand(0).getReg(); in matchNarrowBinopFeedingAnd()
4824 Register AndLHS = MI.getOperand(1).getReg(); in matchNarrowBinopFeedingAnd()
4825 Register AndRHS = MI.getOperand(2).getReg(); in matchNarrowBinopFeedingAnd()
4880 Register BinOpLHS = LHSInst->getOperand(1).getReg(); in matchNarrowBinopFeedingAnd()
4881 Register BinOpRHS = LHSInst->getOperand(2).getReg(); in matchNarrowBinopFeedingAnd()
4919 Register Dst = MI.getOperand(0).getReg(); in matchMulOBy0()
4920 Register Carry = MI.getOperand(1).getReg(); in matchMulOBy0()
4937 Register Carry = MI.getOperand(1).getReg(); in matchAddOBy0()
4940 Register Dst = MI.getOperand(0).getReg(); in matchAddOBy0()
4941 Register LHS = MI.getOperand(2).getReg(); in matchAddOBy0()
4985 Register Dst = MI.getOperand(0).getReg(); in matchSubAddSameReg()
4988 Register X, Y, Z; in matchSubAddSameReg()
4990 Register ReplaceReg; in matchSubAddSameReg()
5007 Register ReplaceReg; in matchSubAddSameReg()
5029 Register Dst = UDiv.getReg(0); in buildUDivUsingMul()
5030 Register LHS = UDiv.getReg(1); in buildUDivUsingMul()
5031 Register RHS = UDiv.getReg(2); in buildUDivUsingMul()
5041 SmallVector<Register, 16> PreShifts, PostShifts, MagicFactors, NPQFactors; in buildUDivUsingMul()
5089 Register PreShift, PostShift, MagicFactor, NPQFactor; in buildUDivUsingMul()
5104 Register Q = LHS; in buildUDivUsingMul()
5111 Register NPQ = MIB.buildSub(Ty, LHS, Q).getReg(0); in buildUDivUsingMul()
5133 Register Dst = MI.getOperand(0).getReg(); in matchUDivByConst()
5134 Register RHS = MI.getOperand(2).getReg(); in matchUDivByConst()
5181 Register Dst = MI.getOperand(0).getReg(); in matchSDivByConst()
5182 Register RHS = MI.getOperand(2).getReg(); in matchSDivByConst()
5216 Register Dst = SDiv.getReg(0); in buildSDivUsingMul()
5217 Register LHS = SDiv.getReg(1); in buildSDivUsingMul()
5218 Register RHS = SDiv.getReg(2); in buildSDivUsingMul()
5227 SmallVector<Register, 16> Shifts, Factors; in buildSDivUsingMul()
5264 Register Shift, Factor; in buildSDivUsingMul()
5273 Register Res = LHS; in buildSDivUsingMul()
5283 Register RHS = MI.getOperand(2).getReg(); in matchUMulHToLShr()
5284 Register Dst = MI.getOperand(0).getReg(); in matchUMulHToLShr()
5298 Register LHS = MI.getOperand(1).getReg(); in applyUMulHToLShr()
5299 Register RHS = MI.getOperand(2).getReg(); in applyUMulHToLShr()
5300 Register Dst = MI.getOperand(0).getReg(); in applyUMulHToLShr()
5321 Register Dst = MI.getOperand(0).getReg(); in matchRedundantNegOperands()
5322 Register X = MI.getOperand(1).getReg(); in matchRedundantNegOperands()
5323 Register Y = MI.getOperand(2).getReg(); in matchRedundantNegOperands()
5360 bool CombinerHelper::matchFsubToFneg(MachineInstr &MI, Register &MatchInfo) { in matchFsubToFneg()
5363 Register LHS = MI.getOperand(1).getReg(); in matchFsubToFneg()
5384 void CombinerHelper::applyFsubToFneg(MachineInstr &MI, Register &MatchInfo) { in applyFsubToFneg()
5386 Register Dst = MI.getOperand(0).getReg(); in applyFsubToFneg()
5449 Register Op1 = MI.getOperand(1).getReg(); in matchCombineFAddFMulToFMadOrFMA()
5450 Register Op2 = MI.getOperand(2).getReg(); in matchCombineFAddFMulToFMadOrFMA()
5498 Register Op1 = MI.getOperand(1).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMA()
5499 Register Op2 = MI.getOperand(2).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMA()
5556 Register Op1 = MI.getOperand(1).getReg(); in matchCombineFAddFMAFMulToFMadOrFMA()
5557 Register Op2 = MI.getOperand(2).getReg(); in matchCombineFAddFMAFMulToFMadOrFMA()
5574 Register Z; in matchCombineFAddFMAFMulToFMadOrFMA()
5596 Register X = FMA->getOperand(1).getReg(); in matchCombineFAddFMAFMulToFMadOrFMA()
5597 Register Y = FMA->getOperand(2).getReg(); in matchCombineFAddFMAFMulToFMadOrFMA()
5598 Register U = FMulMI->getOperand(1).getReg(); in matchCombineFAddFMAFMulToFMadOrFMA()
5599 Register V = FMulMI->getOperand(2).getReg(); in matchCombineFAddFMAFMulToFMadOrFMA()
5602 Register InnerFMA = MRI.createGenericVirtualRegister(DstTy); in matchCombineFAddFMAFMulToFMadOrFMA()
5626 Register Op1 = MI.getOperand(1).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5627 Register Op2 = MI.getOperand(2).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5643 auto buildMatchInfo = [=, &MI](Register U, Register V, Register Z, Register X, in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5644 Register Y, MachineIRBuilder &B) { in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5645 Register FpExtU = B.buildFPExt(DstType, U).getReg(0); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5646 Register FpExtV = B.buildFPExt(DstType, V).getReg(0); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5647 Register InnerFMA = in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5684 Register X = FMAMI->getOperand(1).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5685 Register Y = FMAMI->getOperand(2).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5725 Register X = FMAMI->getOperand(1).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5726 Register Y = FMAMI->getOperand(2).getReg(); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5747 Register Op1 = MI.getOperand(1).getReg(); in matchCombineFSubFMulToFMadOrFMA()
5748 Register Op2 = MI.getOperand(2).getReg(); in matchCombineFSubFMulToFMadOrFMA()
5769 Register NegZ = B.buildFNeg(DstTy, RHS.Reg).getReg(0); in matchCombineFSubFMulToFMadOrFMA()
5780 Register NegY = in matchCombineFSubFMulToFMadOrFMA()
5799 Register LHSReg = MI.getOperand(1).getReg(); in matchCombineFSubFNegFMulToFMadOrFMA()
5800 Register RHSReg = MI.getOperand(2).getReg(); in matchCombineFSubFNegFMulToFMadOrFMA()
5813 Register NegX = in matchCombineFSubFNegFMulToFMadOrFMA()
5815 Register NegZ = B.buildFNeg(DstTy, RHSReg).getReg(0); in matchCombineFSubFNegFMulToFMadOrFMA()
5846 Register LHSReg = MI.getOperand(1).getReg(); in matchCombineFSubFpExtFMulToFMadOrFMA()
5847 Register RHSReg = MI.getOperand(2).getReg(); in matchCombineFSubFpExtFMulToFMadOrFMA()
5859 Register FpExtX = in matchCombineFSubFpExtFMulToFMadOrFMA()
5861 Register FpExtY = in matchCombineFSubFpExtFMulToFMadOrFMA()
5863 Register NegZ = B.buildFNeg(DstTy, RHSReg).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
5875 Register FpExtY = in matchCombineFSubFpExtFMulToFMadOrFMA()
5877 Register NegY = B.buildFNeg(DstTy, FpExtY).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
5878 Register FpExtZ = in matchCombineFSubFpExtFMulToFMadOrFMA()
5899 Register LHSReg = MI.getOperand(1).getReg(); in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5900 Register RHSReg = MI.getOperand(2).getReg(); in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5905 auto buildMatchInfo = [=](Register Dst, Register X, Register Y, Register Z, in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5907 Register FpExtX = B.buildFPExt(DstTy, X).getReg(0); in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5908 Register FpExtY = B.buildFPExt(DstTy, Y).getReg(0); in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5923 Register FMAReg = MRI.createGenericVirtualRegister(DstTy); in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5965 Register MaybeNaNReg = MI.getOperand(Idx).getReg(); in matchCombineFMinMaxNaN()
5976 bool CombinerHelper::matchAddSubSameReg(MachineInstr &MI, Register &Src) { in matchAddSubSameReg()
5978 Register LHS = MI.getOperand(1).getReg(); in matchAddSubSameReg()
5979 Register RHS = MI.getOperand(2).getReg(); in matchAddSubSameReg()
5984 auto CheckFold = [&](Register MaybeSub, Register MaybeSameReg) { in matchAddSubSameReg()
5985 Register Reg; in matchAddSubSameReg()
5993 Register &MatchInfo) { in matchBuildVectorIdentityFold()
6013 Register Lo, Hi; in matchBuildVectorIdentityFold()
6039 Register &MatchInfo) { in matchTruncBuildVectorFold()
6050 Register &MatchInfo) { in matchTruncLshrBuildVectorFold()
6104 CombinerHelper::computeRetValAgainstNaN(Register LHS, Register RHS, in computeRetValAgainstNaN()
6124 bool CombinerHelper::matchFPSelectToMinMax(Register Dst, Register Cond, in matchFPSelectToMinMax()
6125 Register TrueVal, Register FalseVal, in matchFPSelectToMinMax()
6137 Register CmpLHS, CmpRHS; in matchFPSelectToMinMax()
6185 Register Cond = MI.getOperand(1).getReg(); in matchSimplifySelectToMinMax()
6186 Register MaybeTrunc; in matchSimplifySelectToMinMax()
6189 Register Dst = MI.getOperand(0).getReg(); in matchSimplifySelectToMinMax()
6190 Register TrueVal = MI.getOperand(2).getReg(); in matchSimplifySelectToMinMax()
6191 Register FalseVal = MI.getOperand(3).getReg(); in matchSimplifySelectToMinMax()
6204 Register Dst = MI.getOperand(0).getReg(); in matchRedundantBinOpInEquality()
6206 Register X, Y, OpLHS, OpRHS; in matchRedundantBinOpInEquality()
6218 Y = X == OpLHS ? OpRHS : X == OpRHS ? OpLHS : Register(); in matchRedundantBinOpInEquality()
6228 Register ShiftReg = MI.getOperand(2).getReg(); in matchShiftsTooBig()
6238 Register LHS = MI.getOperand(1).getReg(); in matchCommuteConstantToRHS()
6239 Register RHS = MI.getOperand(2).getReg(); in matchCommuteConstantToRHS()
6254 Register LHS = MI.getOperand(1).getReg(); in matchCommuteFPConstantToRHS()
6255 Register RHS = MI.getOperand(2).getReg(); in matchCommuteFPConstantToRHS()
6264 Register LHSReg = MI.getOperand(1).getReg(); in applyCommuteBinOpOperands()
6265 Register RHSReg = MI.getOperand(2).getReg(); in applyCommuteBinOpOperands()
6271 bool CombinerHelper::isOneOrOneSplat(Register Src, bool AllowUndefs) { in isOneOrOneSplat()
6284 bool CombinerHelper::isZeroOrZeroSplat(Register Src, bool AllowUndefs) { in isZeroOrZeroSplat()
6299 bool CombinerHelper::isConstantSplatVector(Register Src, int64_t SplatValue, in isConstantSplatVector()
6325 CombinerHelper::getConstantOrConstantSplatVector(Register Src) { in getConstantOrConstantSplatVector()
6353 Register Dest = Select->getReg(0); in tryFoldSelectOfConstants()
6354 Register Cond = Select->getCondReg(); in tryFoldSelectOfConstants()
6355 Register True = Select->getTrueReg(); in tryFoldSelectOfConstants()
6356 Register False = Select->getFalseReg(); in tryFoldSelectOfConstants()
6398 Register Inner = MRI.createGenericVirtualRegister(CondTy); in tryFoldSelectOfConstants()
6409 Register Inner = MRI.createGenericVirtualRegister(CondTy); in tryFoldSelectOfConstants()
6420 Register Inner = MRI.createGenericVirtualRegister(TrueTy); in tryFoldSelectOfConstants()
6431 Register Inner = MRI.createGenericVirtualRegister(TrueTy); in tryFoldSelectOfConstants()
6442 Register Inner = MRI.createGenericVirtualRegister(TrueTy); in tryFoldSelectOfConstants()
6455 Register Inner = MRI.createGenericVirtualRegister(TrueTy); in tryFoldSelectOfConstants()
6466 Register Not = MRI.createGenericVirtualRegister(CondTy); in tryFoldSelectOfConstants()
6468 Register Inner = MRI.createGenericVirtualRegister(TrueTy); in tryFoldSelectOfConstants()
6482 Register DstReg = Select->getReg(0); in tryFoldBoolSelectToLogic()
6483 Register Cond = Select->getCondReg(); in tryFoldBoolSelectToLogic()
6484 Register True = Select->getTrueReg(); in tryFoldBoolSelectToLogic()
6485 Register False = Select->getFalseReg(); in tryFoldBoolSelectToLogic()
6504 Register Ext = MRI.createGenericVirtualRegister(TrueTy); in tryFoldBoolSelectToLogic()
6516 Register Ext = MRI.createGenericVirtualRegister(TrueTy); in tryFoldBoolSelectToLogic()
6528 Register Inner = MRI.createGenericVirtualRegister(CondTy); in tryFoldBoolSelectToLogic()
6531 Register Ext = MRI.createGenericVirtualRegister(TrueTy); in tryFoldBoolSelectToLogic()
6543 Register Inner = MRI.createGenericVirtualRegister(CondTy); in tryFoldBoolSelectToLogic()
6546 Register Ext = MRI.createGenericVirtualRegister(TrueTy); in tryFoldBoolSelectToLogic()
6558 Register DstReg = Select->getReg(0); in tryFoldSelectToIntMinMax()
6559 Register Cond = Select->getCondReg(); in tryFoldSelectToIntMinMax()
6560 Register True = Select->getTrueReg(); in tryFoldSelectToIntMinMax()
6561 Register False = Select->getFalseReg(); in tryFoldSelectToIntMinMax()
6582 Register CmpLHS = Cmp->getLHSReg(); in tryFoldSelectToIntMinMax()
6583 Register CmpRHS = Cmp->getRHSReg(); in tryFoldSelectToIntMinMax()