Lines Matching refs:Register
112 DenseMap<Register, Register> SrcRegMap;
117 DenseMap<Register, Register> DstRegMap;
119 MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB) const;
121 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
123 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
125 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
129 bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
132 bool isKilled(MachineInstr &MI, Register Reg, bool allowFalsePositives) const;
134 MachineInstr *findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
135 bool &IsCopy, Register &DstReg,
138 bool regsAreCompatible(Register RegA, Register RegB) const;
141 DenseMap<Register, Register> &RegMap) const;
145 bool regOverlapsSet(const SmallVectorImpl<Register> &Set, Register Reg) const;
147 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
153 bool isProfitableToConv3Addr(Register RegA, Register RegB);
156 MachineBasicBlock::iterator &nmi, Register RegA,
157 Register RegB, unsigned &Dist);
159 bool isDefTooClose(Register Reg, unsigned Dist, MachineInstr *MI);
162 MachineBasicBlock::iterator &nmi, Register Reg);
164 MachineBasicBlock::iterator &nmi, Register Reg);
176 void scanUses(Register DstReg);
225 TwoAddressInstructionPass::getSingleDef(Register Reg, in INITIALIZE_PASS_DEPENDENCY()
246 bool TwoAddressInstructionPass::isRevCopyChain(Register FromReg, Register ToReg, in isRevCopyChain()
248 Register TmpReg = FromReg; in isRevCopyChain()
266 bool TwoAddressInstructionPass::noUseAfterLastDef(Register Reg, unsigned Dist, in noUseAfterLastDef()
289 bool TwoAddressInstructionPass::isCopyToReg(MachineInstr &MI, Register &SrcReg, in isCopyToReg()
290 Register &DstReg, bool &IsSrcPhys, in isCopyToReg()
324 Register Reg) const { in isPlainlyKilled()
369 bool TwoAddressInstructionPass::isKilled(MachineInstr &MI, Register Reg, in isKilled()
387 Register SrcReg, DstReg; in isKilled()
398 static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg) { in isTwoAddrUse()
415 Register Reg, MachineBasicBlock *MBB, bool &IsCopy, Register &DstReg, in findOnlyInterestingUse()
429 Register SrcReg; in findOnlyInterestingUse()
457 static MCRegister getMappedReg(Register Reg, in getMappedReg()
458 DenseMap<Register, Register> &RegMap) { in getMappedReg() argument
460 DenseMap<Register, Register>::iterator SI = RegMap.find(Reg); in getMappedReg()
471 bool TwoAddressInstructionPass::regsAreCompatible(Register RegA, in regsAreCompatible()
472 Register RegB) const { in regsAreCompatible()
482 const MachineOperand &MO, DenseMap<Register, Register> &RegMap) const { in removeMapRegEntry() argument
487 SmallVector<Register, 2> Srcs; in removeMapRegEntry()
489 Register ToReg = SI.second; in removeMapRegEntry()
494 Register Reg = MO.getReg(); in removeMapRegEntry()
525 Register Dst = MI->getOperand(0).getReg(); in removeClobberedSrcRegMap()
529 Register Src = MI->getOperand(1).getReg(); in removeClobberedSrcRegMap()
541 Register Reg = MO.getReg(); in removeClobberedSrcRegMap()
550 const SmallVectorImpl<Register> &Set, Register Reg) const { in regOverlapsSet()
560 bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA, in isProfitableToCommute()
561 Register RegB, in isProfitableToCommute()
562 Register RegC, in isProfitableToCommute()
670 Register RegC = MI->getOperand(RegCIdx).getReg(); in commuteInstruction()
687 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
696 bool TwoAddressInstructionPass::isProfitableToConv3Addr(Register RegA, in isProfitableToConv3Addr()
697 Register RegB) { in isProfitableToConv3Addr()
715 Register RegA, Register RegB, unsigned &Dist) { in convertInstTo3Addr()
755 void TwoAddressInstructionPass::scanUses(Register DstReg) { in scanUses()
756 SmallVector<Register, 4> VirtRegPairs; in scanUses()
759 Register NewReg; in scanUses()
760 Register Reg = DstReg; in scanUses()
813 Register SrcReg, DstReg; in processCopy()
836 Register Reg) { in rescheduleMIBelowKill()
873 Register DstReg; in rescheduleMIBelowKill()
885 SmallVector<Register, 2> Uses; in rescheduleMIBelowKill()
886 SmallVector<Register, 2> Kills; in rescheduleMIBelowKill()
887 SmallVector<Register, 2> Defs; in rescheduleMIBelowKill()
891 Register MOReg = MO.getReg(); in rescheduleMIBelowKill()
934 Register MOReg = MO.getReg(); in rescheduleMIBelowKill()
1001 bool TwoAddressInstructionPass::isDefTooClose(Register Reg, unsigned Dist, in isDefTooClose()
1024 Register Reg) { in rescheduleKillAboveMI()
1056 Register DstReg; in rescheduleKillAboveMI()
1064 SmallVector<Register, 2> Uses; in rescheduleKillAboveMI()
1065 SmallVector<Register, 2> Kills; in rescheduleKillAboveMI()
1066 SmallVector<Register, 2> Defs; in rescheduleKillAboveMI()
1067 SmallVector<Register, 2> LiveDefs; in rescheduleKillAboveMI()
1071 Register MOReg = MO.getReg(); in rescheduleKillAboveMI()
1104 SmallVector<Register, 2> OtherDefs; in rescheduleKillAboveMI()
1108 Register MOReg = MO.getReg(); in rescheduleKillAboveMI()
1127 for (Register MOReg : OtherDefs) { in rescheduleKillAboveMI()
1183 Register DstOpReg = MI->getOperand(DstOpIdx).getReg(); in tryInstructionCommute()
1184 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg(); in tryInstructionCommute()
1196 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg(); in tryInstructionCommute()
1248 Register regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1249 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1334 Register Reg = MRI->createVirtualRegister(RC); in tryInstructionTransform()
1396 SmallVector<Register, 4> OrigRegs; in tryInstructionTransform()
1450 Register SrcReg = SrcMO.getReg(); in collectTiedOperands()
1451 Register DstReg = DstMO.getReg(); in collectTiedOperands()
1489 Register RegB = 0; in processTiedPairs()
1496 Register RegA = DstMO.getReg(); in processTiedPairs()
1671 Register RegB = TO.first; in processStatepoint()
1681 Register RegA = DstMO.getReg(); in processStatepoint()
1831 Register SrcReg = mi->getOperand(SrcIdx).getReg(); in runOnMachineFunction()
1832 Register DstReg = mi->getOperand(DstIdx).getReg(); in runOnMachineFunction()
1874 Register Reg = mi->getOperand(0).getReg(); in runOnMachineFunction()
1929 Register DstReg = MI.getOperand(0).getReg(); in eliminateRegSequence()
1931 SmallVector<Register, 4> OrigRegs; in eliminateRegSequence()
1942 Register SrcReg = UseMO.getReg(); in eliminateRegSequence()