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Searched refs:IndexReg (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp511 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optLEAALU()
513 if (AluDestReg == IndexReg) { in optLEAALU()
514 if (BaseReg == IndexReg) in optLEAALU()
516 std::swap(BaseReg, IndexReg); in optLEAALU()
519 if (BaseReg == IndexReg) in optLEAALU()
577 if (IndexReg != 0) in optTwoAddrLEA()
578 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
590 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
765 if (IndexReg != 0) in processInstrForSlow3OpLEA()
766 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
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H A DX86InstrBuilder.h54 unsigned IndexReg; member
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
108 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
H A DX86InsertPrefetch.cpp85 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
89 (IndexReg == 0 || in IsMemOpCompatibleWithPrefetch()
90 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) || in IsMemOpCompatibleWithPrefetch()
91 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)); in IsMemOpCompatibleWithPrefetch()
H A DX86AsmPrinter.cpp378 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
388 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
409 assert(IndexReg.getReg() != X86::ESP && in PrintLeaMemReference()
416 if (IndexReg.getReg()) { in PrintLeaMemReference()
475 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
505 if (IndexReg.getReg()) { in PrintIntelMemReference()
520 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
H A DX86FastISel.cpp217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
816 if (AM.IndexReg == 0) { in handleConstantAddresses()
819 return AM.IndexReg != 0; in handleConstantAddresses()
903 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
935 if (IndexReg == 0 && in X86SelectAddress()
941 if (IndexReg == 0) in X86SelectAddress()
954 AM.IndexReg = IndexReg; in X86SelectAddress()
1112 if (AM.IndexReg == 0) { in X86SelectCallAddress()
1115 return AM.IndexReg != 0; in X86SelectCallAddress()
4023 if (IndexReg == MO.getReg()) in tryToFoldLoadIntoMI()
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H A DX86ISelDAGToDAG.cpp70 SDValue IndexReg; member
123 if (IndexReg.getNode()) in dump()
286 AM.IndexReg = Neg; in getAddressOperands()
290 Index = AM.IndexReg; in getAddressOperands()
2026 AM.IndexReg = Ext; in foldMaskAndShiftToExtract()
2095 AM.IndexReg = NewAnd; in foldMaskedShiftToScaledMask()
2211 AM.IndexReg = NewExt; in foldMaskAndShiftToScale()
2275 AM.IndexReg = NewExt; in foldMaskedShiftToBEXTR()
2612 AM.IndexReg = RHS; in matchAddressRecursively()
2736 AM.IndexReg = Zext; in matchAddressRecursively()
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H A DX86SpeculativeLoadHardening.cpp1335 unsigned BaseReg = 0, IndexReg = 0; in tracePredStateThroughBlocksAndHarden() local
1340 IndexReg = IndexMO.getReg(); in tracePredStateThroughBlocksAndHarden()
1342 if (!BaseReg && !IndexReg) in tracePredStateThroughBlocksAndHarden()
1351 (IndexReg && LoadDepRegs.test(IndexReg))) in tracePredStateThroughBlocksAndHarden()
1364 !HardenedAddrRegs.count(IndexReg)) { in tracePredStateThroughBlocksAndHarden()
1375 if (IndexReg) in tracePredStateThroughBlocksAndHarden()
1376 HardenedAddrRegs.insert(IndexReg); in tracePredStateThroughBlocksAndHarden()
H A DX86MCInstLower.cpp654 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in emitNop() local
655 IndexReg = Displacement = SegmentReg = 0; in emitNop()
683 IndexReg = X86::RAX; in emitNop()
689 IndexReg = X86::RAX; in emitNop()
700 IndexReg = X86::RAX; in emitNop()
706 IndexReg = X86::RAX; in emitNop()
712 IndexReg = X86::RAX; in emitNop()
736 .addReg(IndexReg) in emitNop()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h67 unsigned IndexReg; member
147 if (Mem.IndexReg) in print()
203 return Mem.IndexReg; in getMemIndexReg()
340 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
360 return isMem64() && X86II::isXMMReg(Mem.IndexReg); in isMem64_RC128X()
363 return isMem128() && X86II::isXMMReg(Mem.IndexReg); in isMem128_RC128X()
366 return isMem128() && X86II::isYMMReg(Mem.IndexReg); in isMem128_RC256X()
369 return isMem256() && X86II::isXMMReg(Mem.IndexReg); in isMem256_RC128X()
372 return isMem256() && X86II::isYMMReg(Mem.IndexReg); in isMem256_RC256X()
725 Res->Mem.IndexReg = 0;
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H A DX86AsmParser.cpp684 if (IndexReg) in onPlus()
743 if (IndexReg) in onMinus()
802 if (IndexReg) in onRegister()
884 if (IndexReg) in onInteger()
1311 if (IndexReg != 0 && in CheckBaseRegAndIndexRegAndScale()
1312 !(IndexReg == X86::EIZ || IndexReg == X86::RIZ || in CheckBaseRegAndIndexRegAndScale()
1324 IndexReg == X86::EIP || IndexReg == X86::RIP || in CheckBaseRegAndIndexRegAndScale()
1325 IndexReg == X86::ESP || IndexReg == X86::RSP) { in CheckBaseRegAndIndexRegAndScale()
1367 (IndexReg != X86::SI && IndexReg != X86::DI)) { in CheckBaseRegAndIndexRegAndScale()
2597 (IndexReg == X86::ESP || IndexReg == X86::RSP)) in parseIntelOperand()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h41 Register IndexReg; variable
48 Register getIndex() { return IndexReg; } in getIndex()
49 Register getIndex() const { return IndexReg; } in getIndex()
51 void setIndex(Register NewIndex) { IndexReg = NewIndex; } in setIndex()
H A DMachineIRBuilder.h837 Register IndexReg);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp70 SDValue IndexReg; member
104 return BaseType == Base::RegBase && IndexReg.getNode() != nullptr; in hasIndexReg()
148 void setIndexReg(SDValue Reg) { IndexReg = Reg; } in setIndexReg()
161 if (IndexReg.getNode()) { in dump()
162 IndexReg.getNode()->dump(); in dump()
412 AM.IndexReg = N; in matchAddressBase()
555 AM.IndexReg = N.getOperand(1); in matchADD()
793 if (!isAddressBase(AM.BaseReg) && isAddressBase(AM.IndexReg)) { in SelectARII()
794 Base = AM.IndexReg; in SelectARII()
798 Index = AM.IndexReg; in SelectARII()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp185 unsigned IndexReg; member
367 return Mem.IndexReg; in getMemIndexReg()
698 Op->Mem.IndexReg = 0; in MorphToMEMri()
709 Op->Mem.IndexReg = 0; in MorphToMEMzi()
720 Op->Mem.IndexReg = Index; in MorphToMEMrri()
732 Op->Mem.IndexReg = 0; in MorphToMEMrii()
743 Op->Mem.IndexReg = Index; in MorphToMEMzri()
754 Op->Mem.IndexReg = 0; in MorphToMEMzii()
1253 MCRegister IndexReg; in parseMEMOperand() local
1257 if (parseRegister(IndexReg, S, E)) in parseMEMOperand()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h69 StringRef IndexReg; member
77 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
83 bool hasIndexReg() const { return !IndexReg.empty(); } in hasIndexReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.cpp427 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
437 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
444 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
449 if (IndexReg.getReg()) { in printMemReference()
H A DX86MCCodeEmitter.cpp606 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() local
614 assert(IndexReg.getReg() == 0 && !ForceSIB && in emitMemModRMByte()
705 if (IndexReg.getReg()) { in emitMemModRMByte()
706 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)]; in emitMemModRMByte()
736 assert(IndexReg.getReg() == 0 && "Unexpected index register!"); in emitMemModRMByte()
758 !ForceSIB && IndexReg.getReg() == 0 && in emitMemModRMByte()
824 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && in emitMemModRMByte()
861 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4; in emitMemModRMByte()
H A DX86IntelInstPrinter.cpp385 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
400 if (IndexReg.getReg()) { in printMemReference()
414 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
H A DX86MCTargetDesc.cpp666 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() local
669 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || in evaluateMemoryOperandAddress()
692 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset() local
697 IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm()) in getMemoryOperandRelocationOffset()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp166 unsigned &IndexReg);
420 unsigned &IndexReg) { in PPCSimplifyAddress() argument
440 IndexReg = PPCMaterializeInt(Offset, MVT::i64); in PPCSimplifyAddress()
504 unsigned IndexReg = 0; in PPCEmitLoad() local
505 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitLoad()
577 if (IndexReg) in PPCEmitLoad()
578 MIB.addReg(Addr.Base.Reg).addReg(IndexReg); in PPCEmitLoad()
653 unsigned IndexReg = 0; in PPCEmitStore() local
654 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitStore()
723 if (IndexReg) in PPCEmitStore()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp339 Register IndexReg = 0; in emitInstruction() local
342 IndexReg = TargetReg; in emitInstruction()
358 .addReg(IndexReg)); in emitInstruction()
H A DSystemZISelLowering.cpp968 bool IndexReg; member
971 LongDisplacement(LongDispl), IndexReg(IdxReg) {} in AddressingMode()
1079 if (!SupportedAM.IndexReg) in isLegalAddressingMode()
8243 Register IndexReg = MI.getOperand(3).getReg(); in emitCondStore() local
8262 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) { in emitCondStore()
8310 .addReg(IndexReg) in emitCondStore()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp296 Register IndexReg) { in buildBrJT() argument
302 .addUse(IndexReg); in buildBrJT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp666 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in selectGlobalValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/MCParser/
H A DAsmParser.cpp6152 << AR.IntelExp.IndexReg; in parseMSInlineAsm()

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