431     unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0;  member in __anonb23049e20111::X86AsmParser::IntelExprStateMachine
466     unsigned getIndexReg() const { return IndexReg; }  in getIndexReg()
684             if (IndexReg)  in onPlus()
686             IndexReg = TmpReg;  in onPlus()
743             if (IndexReg)  in onMinus()
745             IndexReg = TmpReg;  in onMinus()
802           if (IndexReg)  in onRegister()
805           IndexReg = Reg;  in onRegister()
884           if (IndexReg)  in onInteger()
886           IndexReg = TmpReg;  in onInteger()
988             if (IndexReg)  in onRBrac()
990             IndexReg = TmpReg;  in onRBrac()
1146                                unsigned BaseReg, unsigned IndexReg,
1295 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1311   if (IndexReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1312       !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||  in CheckBaseRegAndIndexRegAndScale()
1313         X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1314         X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1315         X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1316         X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1317         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1318         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {  in CheckBaseRegAndIndexRegAndScale()
1323   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1324       IndexReg == X86::EIP || IndexReg == X86::RIP ||  in CheckBaseRegAndIndexRegAndScale()
1325       IndexReg == X86::ESP || IndexReg == X86::RSP) {  in CheckBaseRegAndIndexRegAndScale()
1340       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1345   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1347         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1348          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1349          IndexReg == X86::EIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1354         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1355          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1356          IndexReg == X86::RIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1361       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1362           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1367           (IndexReg != X86::SI && IndexReg != X86::DI)) {  in CheckBaseRegAndIndexRegAndScale()
1749                                            unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1780     if (BaseReg || IndexReg) {  in CreateMemForMSInlineAsm()
1783                                                BaseReg && IndexReg));  in CreateMemForMSInlineAsm()
1790       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2589   unsigned IndexReg = SM.getIndexReg();  in parseIntelOperand()  local
2590   if (IndexReg && BaseReg == X86::RIP)  in parseIntelOperand()
2597       (IndexReg == X86::ESP || IndexReg == X86::RSP))  in parseIntelOperand()
2598     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2603       !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in parseIntelOperand()
2604         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in parseIntelOperand()
2605         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&  in parseIntelOperand()
2609     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2612       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))  in parseIntelOperand()
2623       (IndexReg == X86::BX || IndexReg == X86::BP))  in parseIntelOperand()
2624     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2626   if ((BaseReg || IndexReg) &&  in parseIntelOperand()
2627       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in parseIntelOperand()
2633     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale,  in parseIntelOperand()
2652       } else if (!BaseReg && !IndexReg && Disp &&  in parseIntelOperand()
2674   if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))  in parseIntelOperand()
2676         getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,  in parseIntelOperand()
2977   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
3016         IndexReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
3021         if (IndexReg == X86::RIP)  in ParseMemOperand()
3054   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
3061   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
3070   if (BaseReg || IndexReg) {  in ParseMemOperand()
3074                   X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg);  in ParseMemOperand()
3094   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
3096                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()