Lines Matching refs:IndexReg

459   Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg();  in checkRegUsage()  local
475 if (TRI->regsOverlap(Reg, IndexReg)) { in checkRegUsage()
508 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU() local
511 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optLEAALU()
513 if (AluDestReg == IndexReg) { in optLEAALU()
514 if (BaseReg == IndexReg) in optLEAALU()
516 std::swap(BaseReg, IndexReg); in optLEAALU()
519 if (BaseReg == IndexReg) in optLEAALU()
533 .addReg(IndexReg, KilledIndex ? RegState::Kill : 0); in optLEAALU()
567 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
577 if (IndexReg != 0) in optTwoAddrLEA()
578 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
586 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
587 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
590 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
595 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
600 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
602 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
634 } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) { in optTwoAddrLEA()
760 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
765 if (IndexReg != 0) in processInstrForSlow3OpLEA()
766 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
771 bool IsInefficientIndex = isInefficientLEAReg(IndexReg); in processInstrForSlow3OpLEA()
782 bool BaseOrIndexIsDst = DestReg == BaseReg || DestReg == IndexReg; in processInstrForSlow3OpLEA()
789 if (IsScale1 && BaseReg == IndexReg && in processInstrForSlow3OpLEA()
812 std::swap(BaseReg, IndexReg); in processInstrForSlow3OpLEA()
818 .addReg(IndexReg) in processInstrForSlow3OpLEA()
824 .addReg(IndexReg); in processInstrForSlow3OpLEA()
878 bool BIK = Base.isKill() && BaseReg != IndexReg; in processInstrForSlow3OpLEA()