Lines Matching refs:IndexReg
217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
734 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { in handleConstantAddresses()
753 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in handleConstantAddresses()
816 if (AM.IndexReg == 0) { in handleConstantAddresses()
818 AM.IndexReg = getRegForValue(V); in handleConstantAddresses()
819 return AM.IndexReg != 0; in handleConstantAddresses()
903 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
935 if (IndexReg == 0 && in X86SelectAddress()
940 IndexReg = getRegForGEPIndex(Op); in X86SelectAddress()
941 if (IndexReg == 0) in X86SelectAddress()
954 AM.IndexReg = IndexReg; in X86SelectAddress()
1058 (AM.Base.Reg != 0 || AM.IndexReg != 0)) in X86SelectCallAddress()
1075 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in X86SelectCallAddress()
1112 if (AM.IndexReg == 0) { in X86SelectCallAddress()
1114 AM.IndexReg = GetCallRegForValue(V); in X86SelectCallAddress()
1115 return AM.IndexReg != 0; in X86SelectCallAddress()
3860 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr) in X86MaterializeGV()
4018 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg) in tryToFoldLoadIntoMI()
4021 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI() local
4023 if (IndexReg == MO.getReg()) in tryToFoldLoadIntoMI()
4025 MO.setReg(IndexReg); in tryToFoldLoadIntoMI()